Merge pull request #1397 from dp-arm/dp/cortex-a76
Add support for Cortex-A76 and Cortex-Ares
This commit is contained in:
Dimitris Papastamos
GitHub
commit
608529aa24
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@ -0,0 +1,29 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CORTEX_A76_H__
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#define __CORTEX_A76_H__
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/* Cortex-A76 MIDR for revision 0 */
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#define CORTEX_A76_MIDR 0x410fd0b0
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (1 << 16)
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/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */
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#define CORTEX_A76_CORE_PWRDN_EN_MASK 0x1
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#endif /* __CORTEX_A76_H__ */
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@ -0,0 +1,33 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CORTEX_ARES_H__
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#define __CORTEX_ARES_H__
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/* Cortex-ARES MIDR for revision 0 */
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#define CORTEX_ARES_MIDR 0x410fd0c0
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4
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/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */
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#define CORTEX_ARES_CORE_PWRDN_EN_MASK 0x1
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#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4)
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#define CORTEX_ARES_AMU_NR_COUNTERS U(5)
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#define CORTEX_ARES_AMU_GROUP0_MASK U(0x1f)
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/* Instruction patching registers */
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#define CPUPSELR_EL3 S3_6_C15_C8_0
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#define CPUPCR_EL3 S3_6_C15_C8_1
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#define CPUPOR_EL3 S3_6_C15_C8_2
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#define CPUPMR_EL3 S3_6_C15_C8_3
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#endif /* __CORTEX_ARES_H__ */
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@ -271,6 +271,7 @@ typedef struct cpu_context {
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#endif
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#define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx)
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#define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx)
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#define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx)
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/*
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* Compile time assertions related to the 'cpu_context' structure to
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@ -0,0 +1,290 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arm_arch_svc.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <context.h>
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#include <cortex_a76.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#if !DYNAMIC_WORKAROUND_CVE_2018_3639
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#error Cortex A76 requires DYNAMIC_WORKAROUND_CVE_2018_3639=1
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#endif
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#define ESR_EL3_A64_SMC0 0x5e000000
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#define ESR_EL3_A32_SMC0 0x4e000000
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/*
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* This macro applies the mitigation for CVE-2018-3639.
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* It implements a fash path where `SMCCC_ARCH_WORKAROUND_2`
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* SMC calls from a lower EL running in AArch32 or AArch64
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* will go through the fast and return early.
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*
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* The macro saves x2-x3 to the context. In the fast path
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* x0-x3 registers do not need to be restored as the calling
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* context will have saved them.
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*/
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.macro apply_cve_2018_3639_wa _is_sync_exception _esr_el3_val
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stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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.if \_is_sync_exception
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/*
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* Ensure SMC is coming from A64/A32 state on #0
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* with W0 = SMCCC_ARCH_WORKAROUND_2
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*
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* This sequence evaluates as:
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* (W0==SMCCC_ARCH_WORKAROUND_2) ? (ESR_EL3==SMC#0) : (NE)
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* allowing use of a single branch operation
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*/
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orr w2, wzr, #SMCCC_ARCH_WORKAROUND_2
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cmp x0, x2
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mrs x3, esr_el3
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mov_imm w2, \_esr_el3_val
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ccmp w2, w3, #0, eq
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/*
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* Static predictor will predict a fall-through, optimizing
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* the `SMCCC_ARCH_WORKAROUND_2` fast path.
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*/
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bne 1f
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/*
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* The sequence below implements the `SMCCC_ARCH_WORKAROUND_2`
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* fast path.
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*/
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cmp x1, xzr /* enable/disable check */
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/*
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* When the calling context wants mitigation disabled,
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* we program the mitigation disable function in the
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* CPU context, which gets invoked on subsequent exits from
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* EL3 via the `el3_exit` function. Otherwise NULL is
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* programmed in the CPU context, which results in caller's
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* inheriting the EL3 mitigation state (enabled) on subsequent
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* `el3_exit`.
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*/
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mov x0, xzr
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adr x1, cortex_a76_disable_wa_cve_2018_3639
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csel x1, x1, x0, eq
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str x1, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE]
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mrs x2, CORTEX_A76_CPUACTLR2_EL1
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orr x1, x2, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
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bic x3, x2, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
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csel x3, x3, x1, eq
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msr CORTEX_A76_CPUACTLR2_EL1, x3
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eret /* ERET implies ISB */
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.endif
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1:
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/*
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* Always enable v4 mitigation during EL3 execution. This is not
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* required for the fast path above because it does not perform any
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* memory loads.
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*/
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mrs x2, CORTEX_A76_CPUACTLR2_EL1
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orr x2, x2, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
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msr CORTEX_A76_CPUACTLR2_EL1, x2
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isb
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/*
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* The caller may have passed arguments to EL3 via x2-x3.
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* Restore these registers from the context before jumping to the
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* main runtime vector table entry.
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*/
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ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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.endm
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vector_base cortex_a76_wa_cve_2018_3639_a76_vbar
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/* ---------------------------------------------------------------------
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* Current EL with SP_EL0 : 0x0 - 0x200
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* ---------------------------------------------------------------------
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*/
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vector_entry cortex_a76_sync_exception_sp_el0
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b sync_exception_sp_el0
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check_vector_size cortex_a76_sync_exception_sp_el0
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vector_entry cortex_a76_irq_sp_el0
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b irq_sp_el0
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check_vector_size cortex_a76_irq_sp_el0
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vector_entry cortex_a76_fiq_sp_el0
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b fiq_sp_el0
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check_vector_size cortex_a76_fiq_sp_el0
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vector_entry cortex_a76_serror_sp_el0
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b serror_sp_el0
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check_vector_size cortex_a76_serror_sp_el0
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/* ---------------------------------------------------------------------
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* Current EL with SP_ELx: 0x200 - 0x400
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* ---------------------------------------------------------------------
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*/
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vector_entry cortex_a76_sync_exception_sp_elx
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b sync_exception_sp_elx
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check_vector_size cortex_a76_sync_exception_sp_elx
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vector_entry cortex_a76_irq_sp_elx
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b irq_sp_elx
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check_vector_size cortex_a76_irq_sp_elx
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vector_entry cortex_a76_fiq_sp_elx
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b fiq_sp_elx
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check_vector_size cortex_a76_fiq_sp_elx
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vector_entry cortex_a76_serror_sp_elx
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b serror_sp_elx
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check_vector_size cortex_a76_serror_sp_elx
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/* ---------------------------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* ---------------------------------------------------------------------
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*/
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vector_entry cortex_a76_sync_exception_aarch64
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apply_cve_2018_3639_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A64_SMC0
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b sync_exception_aarch64
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check_vector_size cortex_a76_sync_exception_aarch64
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vector_entry cortex_a76_irq_aarch64
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apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
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b irq_aarch64
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check_vector_size cortex_a76_irq_aarch64
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vector_entry cortex_a76_fiq_aarch64
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apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
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b fiq_aarch64
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check_vector_size cortex_a76_fiq_aarch64
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vector_entry cortex_a76_serror_aarch64
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apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
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b serror_aarch64
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check_vector_size cortex_a76_serror_aarch64
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/* ---------------------------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* ---------------------------------------------------------------------
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*/
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vector_entry cortex_a76_sync_exception_aarch32
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apply_cve_2018_3639_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A32_SMC0
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b sync_exception_aarch32
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check_vector_size cortex_a76_sync_exception_aarch32
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vector_entry cortex_a76_irq_aarch32
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apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
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b irq_aarch32
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check_vector_size cortex_a76_irq_aarch32
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vector_entry cortex_a76_fiq_aarch32
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apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
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b fiq_aarch32
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check_vector_size cortex_a76_fiq_aarch32
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vector_entry cortex_a76_serror_aarch32
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apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
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b serror_aarch32
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check_vector_size cortex_a76_serror_aarch32
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func check_errata_cve_2018_3639
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#if WORKAROUND_CVE_2018_3639
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2018_3639
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func cortex_a76_disable_wa_cve_2018_3639
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mrs x0, CORTEX_A76_CPUACTLR2_EL1
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bic x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
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msr CORTEX_A76_CPUACTLR2_EL1, x0
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isb
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ret
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endfunc cortex_a76_disable_wa_cve_2018_3639
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func cortex_a76_reset_func
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#if WORKAROUND_CVE_2018_3639
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mrs x0, CORTEX_A76_CPUACTLR2_EL1
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orr x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
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msr CORTEX_A76_CPUACTLR2_EL1, x0
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isb
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2018_3639
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/*
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* The Cortex-A76 generic vectors are overwritten to use the vectors
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* defined above. This is required in order to apply mitigation
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* against CVE-2018-3639 on exception entry from lower ELs.
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*/
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adr x0, cortex_a76_wa_cve_2018_3639_a76_vbar
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msr vbar_el3, x0
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isb
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#endif
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ret
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endfunc cortex_a76_reset_func
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a76_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A76_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A76_CORE_PWRDN_EN_MASK
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msr CORTEX_A76_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a76_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex Cortex A76. Must follow AAPCS.
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*/
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func cortex_a76_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a76_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_a76 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a76_regs, "aS"
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cortex_a76_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a76_cpu_reg_dump
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adr x6, cortex_a76_regs
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mrs x8, CORTEX_A76_CPUECTLR_EL1
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ret
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endfunc cortex_a76_cpu_reg_dump
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declare_cpu_ops_wa cortex_a76, CORTEX_A76_MIDR, \
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cortex_a76_reset_func, \
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CPU_NO_EXTRA1_FUNC, \
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cortex_a76_disable_wa_cve_2018_3639, \
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cortex_a76_core_pwr_dwn
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@ -0,0 +1,136 @@
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/*
|
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
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*/
|
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|
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#include <arch.h>
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#include <asm_macros.S>
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#include <cortex_ares.h>
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#include <cpuamu.h>
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#include <cpu_macros.S>
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/* --------------------------------------------------
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* Errata Workaround for Cortex-Ares Errata
|
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* This applies to revision r0p0 and r1p0 of Cortex-Ares.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_ares_1043202_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1043202
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cbz x0, 1f
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/* Apply instruction patching sequence */
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ldr x0, =0x0
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msr CPUPSELR_EL3, x0
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ldr x0, =0xF3BF8F2F
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msr CPUPOR_EL3, x0
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ldr x0, =0xFFFFFFFF
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msr CPUPMR_EL3, x0
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ldr x0, =0x800200071
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msr CPUPCR_EL3, x0
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isb
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1:
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ret x17
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endfunc errata_ares_1043202_wa
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func check_errata_1043202
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1043202
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func cortex_ares_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_ARES_1043202
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mov x0, x18
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bl errata_ares_1043202_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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orr x0, x0, #CORTEX_ARES_ACTLR_AMEN_BIT
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msr actlr_el3, x0
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isb
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
|
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mrs x0, actlr_el2
|
||||
orr x0, x0, #CORTEX_ARES_ACTLR_AMEN_BIT
|
||||
msr actlr_el2, x0
|
||||
isb
|
||||
|
||||
/* Enable group0 counters */
|
||||
mov x0, #CORTEX_ARES_AMU_GROUP0_MASK
|
||||
msr CPUAMCNTENSET_EL0, x0
|
||||
isb
|
||||
#endif
|
||||
ret x19
|
||||
endfunc cortex_ares_reset_func
|
||||
|
||||
/* ---------------------------------------------
|
||||
* HW will do the cache maintenance while powering down
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func cortex_ares_core_pwr_dwn
|
||||
/* ---------------------------------------------
|
||||
* Enable CPU power down bit in power control register
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1
|
||||
orr x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK
|
||||
msr CORTEX_ARES_CPUPWRCTLR_EL1, x0
|
||||
isb
|
||||
ret
|
||||
endfunc cortex_ares_core_pwr_dwn
|
||||
|
||||
#if REPORT_ERRATA
|
||||
/*
|
||||
* Errata printing function for Cortex-Ares. Must follow AAPCS.
|
||||
*/
|
||||
func cortex_a72_errata_report
|
||||
stp x8, x30, [sp, #-16]!
|
||||
|
||||
bl cpu_get_rev_var
|
||||
mov x8, x0
|
||||
|
||||
/*
|
||||
* Report all errata. The revision-variant information is passed to
|
||||
* checking functions of each errata.
|
||||
*/
|
||||
report_errata ERRATA_ARES_1043202, cortex_ares, 1043202
|
||||
|
||||
ldp x8, x30, [sp], #16
|
||||
ret
|
||||
endfunc cortex_a72_errata_report
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------
|
||||
* This function provides cortex_ares specific
|
||||
* register information for crash reporting.
|
||||
* It needs to return with x6 pointing to
|
||||
* a list of register names in ascii and
|
||||
* x8 - x15 having values of registers to be
|
||||
* reported.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.section .rodata.cortex_ares_regs, "aS"
|
||||
cortex_ares_regs: /* The ascii list of register names to be reported */
|
||||
.asciz "cpuectlr_el1", ""
|
||||
|
||||
func cortex_ares_cpu_reg_dump
|
||||
adr x6, cortex_ares_regs
|
||||
mrs x8, CORTEX_ARES_CPUECTLR_EL1
|
||||
ret
|
||||
endfunc cortex_ares_cpu_reg_dump
|
||||
|
||||
declare_cpu_ops cortex_ares, CORTEX_ARES_MIDR, \
|
||||
cortex_ares_reset_func, \
|
||||
cortex_ares_core_pwr_dwn
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <cortex_ares.h>
|
||||
#include <cpuamu.h>
|
||||
#include <pubsub_events.h>
|
||||
|
||||
static void *cortex_ares_context_save(const void *arg)
|
||||
{
|
||||
if (midr_match(CORTEX_ARES_MIDR) != 0)
|
||||
cpuamu_context_save(CORTEX_ARES_AMU_NR_COUNTERS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void *cortex_ares_context_restore(const void *arg)
|
||||
{
|
||||
if (midr_match(CORTEX_ARES_MIDR) != 0)
|
||||
cpuamu_context_restore(CORTEX_ARES_AMU_NR_COUNTERS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, cortex_ares_context_save);
|
||||
SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, cortex_ares_context_restore);
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
|
||||
# Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
|
@ -119,6 +119,10 @@ ERRATA_A57_859972 ?=0
|
|||
# only to revision <= r0p3 of the Cortex A72 cpu.
|
||||
ERRATA_A72_859971 ?=0
|
||||
|
||||
# Flag to apply T32 CLREX workaround during reset. This erratum applies
|
||||
# only to r0p0 and r1p0 of the Ares cpu.
|
||||
ERRATA_ARES_1043202 ?=1
|
||||
|
||||
# Process ERRATA_A53_826319 flag
|
||||
$(eval $(call assert_boolean,ERRATA_A53_826319))
|
||||
$(eval $(call add_define,ERRATA_A53_826319))
|
||||
|
|
@ -179,6 +183,10 @@ $(eval $(call add_define,ERRATA_A57_859972))
|
|||
$(eval $(call assert_boolean,ERRATA_A72_859971))
|
||||
$(eval $(call add_define,ERRATA_A72_859971))
|
||||
|
||||
# Process ERRATA_ARES_1043202 flag
|
||||
$(eval $(call assert_boolean,ERRATA_ARES_1043202))
|
||||
$(eval $(call add_define,ERRATA_ARES_1043202))
|
||||
|
||||
# Errata build flags
|
||||
ifneq (${ERRATA_A53_843419},0)
|
||||
TF_LDFLAGS_aarch64 += --fix-cortex-a53-843419
|
||||
|
|
|
|||
|
|
@ -114,7 +114,9 @@ FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
|
|||
lib/cpus/aarch64/cortex_a57.S \
|
||||
lib/cpus/aarch64/cortex_a72.S \
|
||||
lib/cpus/aarch64/cortex_a73.S \
|
||||
lib/cpus/aarch64/cortex_a75.S
|
||||
lib/cpus/aarch64/cortex_a75.S \
|
||||
lib/cpus/aarch64/cortex_a76.S \
|
||||
lib/cpus/aarch64/cortex_ares.S
|
||||
else
|
||||
FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S
|
||||
endif
|
||||
|
|
@ -204,8 +206,12 @@ ENABLE_PLAT_COMPAT := 0
|
|||
# Enable Activity Monitor Unit extensions by default
|
||||
ENABLE_AMU := 1
|
||||
|
||||
# Enable dynamic mitigation support by default
|
||||
DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
|
||||
|
||||
ifeq (${ENABLE_AMU},1)
|
||||
BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \
|
||||
lib/cpus/aarch64/cortex_ares_pubsub.c \
|
||||
lib/cpus/aarch64/cpuamu.c \
|
||||
lib/cpus/aarch64/cpuamu_helpers.S
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -39,6 +39,11 @@ typedef struct sdei_dispatch_context {
|
|||
/* Exception state registers */
|
||||
uint64_t elr_el3;
|
||||
uint64_t spsr_el3;
|
||||
|
||||
#if DYNAMIC_WORKAROUND_CVE_2018_3639
|
||||
/* CVE-2018-3639 mitigation state */
|
||||
uint64_t disable_cve_2018_3639;
|
||||
#endif
|
||||
} sdei_dispatch_context_t;
|
||||
|
||||
/* Per-CPU SDEI state data */
|
||||
|
|
@ -170,6 +175,18 @@ static void save_event_ctx(sdei_ev_map_t *map, void *tgt_ctx, int sec_state,
|
|||
memcpy(disp_ctx->x, tgt_gpregs, sizeof(disp_ctx->x));
|
||||
disp_ctx->spsr_el3 = read_ctx_reg(tgt_el3, CTX_SPSR_EL3);
|
||||
disp_ctx->elr_el3 = read_ctx_reg(tgt_el3, CTX_ELR_EL3);
|
||||
|
||||
#if DYNAMIC_WORKAROUND_CVE_2018_3639
|
||||
cve_2018_3639_t *tgt_cve_2018_3639;
|
||||
tgt_cve_2018_3639 = get_cve_2018_3639_ctx(tgt_ctx);
|
||||
|
||||
/* Save CVE-2018-3639 mitigation state */
|
||||
disp_ctx->disable_cve_2018_3639 = read_ctx_reg(tgt_cve_2018_3639,
|
||||
CTX_CVE_2018_3639_DISABLE);
|
||||
|
||||
/* Force SDEI handler to execute with mitigation enabled by default */
|
||||
write_ctx_reg(tgt_cve_2018_3639, CTX_CVE_2018_3639_DISABLE, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void restore_event_ctx(sdei_dispatch_context_t *disp_ctx, void *tgt_ctx)
|
||||
|
|
@ -188,6 +205,15 @@ static void restore_event_ctx(sdei_dispatch_context_t *disp_ctx, void *tgt_ctx)
|
|||
memcpy(tgt_gpregs, disp_ctx->x, sizeof(disp_ctx->x));
|
||||
write_ctx_reg(tgt_el3, CTX_SPSR_EL3, disp_ctx->spsr_el3);
|
||||
write_ctx_reg(tgt_el3, CTX_ELR_EL3, disp_ctx->elr_el3);
|
||||
|
||||
#if DYNAMIC_WORKAROUND_CVE_2018_3639
|
||||
cve_2018_3639_t *tgt_cve_2018_3639;
|
||||
tgt_cve_2018_3639 = get_cve_2018_3639_ctx(tgt_ctx);
|
||||
|
||||
/* Restore CVE-2018-3639 mitigation state */
|
||||
write_ctx_reg(tgt_cve_2018_3639, CTX_CVE_2018_3639_DISABLE,
|
||||
disp_ctx->disable_cve_2018_3639);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void save_secure_context(void)
|
||||
|
|
|
|||
Loading…
Reference in New Issue