xlat: Add support for EL0 and EL1 mappings
This patch introduces the ability of the xlat tables library to manage EL0 and EL1 mappings from a higher exception level. Attributes MT_USER and MT_PRIVILEGED have been added to allow the user specify the target EL in the translation regime EL1&0. REGISTER_XLAT_CONTEXT2 macro is introduced to allow creating a xlat_ctx_t that targets a given translation regime (EL1&0 or EL3). A new member is added to xlat_ctx_t to represent the translation regime the xlat_ctx_t manages. The execute_never mask member is removed as it is computed from existing information. Change-Id: I95e14abc3371d7a6d6a358cc54c688aa9975c110 Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Antonio Nino Diaz
parent
b4ae615bd7
commit
609c91917f
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@ -77,8 +77,11 @@ might create new translation tables, update or split existing ones.
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The region attributes specify the type of memory (for example device or cached
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normal memory) as well as the memory access permissions (read-only or
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read-write, executable or not, secure or non-secure, and so on). See the
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``mmap_attr_t`` enumeration type in `xlat\_tables\_v2.h`_.
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read-write, executable or not, secure or non-secure, and so on). In the case of
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the EL1&0 translation regime, the attributes also specify whether the region is
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a User region (EL0) or Privileged region (EL1). See the ``mmap_attr_t``
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enumeration type in `xlat\_tables\_v2.h`_. Note that for the EL1&0 translation
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regime the Execute Never attribute is set simultaneously for both EL1 and EL0.
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The granularity controls the translation table level to go down to when mapping
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the region. For example, assuming the MMU has been configured to use a 4KB
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@ -89,9 +89,22 @@
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* AP[1] bit is ignored by hardware and is
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* treated as if it is One in EL2/EL3
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*/
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#define AP_RO (U(0x1) << 5)
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#define AP_RW (U(0x0) << 5)
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#define AP2_SHIFT U(0x7)
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#define AP2_RO U(0x1)
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#define AP2_RW U(0x0)
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#define AP1_SHIFT U(0x6)
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#define AP1_ACCESS_UNPRIVILEGED U(0x1)
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#define AP1_NO_ACCESS_UNPRIVILEGED U(0x0)
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/*
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* The following definitions must all be passed to the LOWER_ATTRS() macro to
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* get the right bitmask.
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*/
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#define AP_RO (AP2_RO << 5)
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#define AP_RW (AP2_RW << 5)
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#define AP_ACCESS_UNPRIVILEGED (AP1_ACCESS_UNPRIVILEGED << 4)
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#define AP_NO_ACCESS_UNPRIVILEGED (AP1_NO_ACCESS_UNPRIVILEGED << 4)
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#define NS (U(0x1) << 3)
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#define ATTR_NON_CACHEABLE_INDEX U(0x2)
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#define ATTR_DEVICE_INDEX U(0x1)
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@ -57,6 +57,11 @@
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#define MT_SEC_SHIFT U(4)
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/* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */
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#define MT_EXECUTE_SHIFT U(5)
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/*
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* In the EL1&0 translation regime, mark the region as User (EL0) or
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* Privileged (EL1). In the EL3 translation regime this has no effect.
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*/
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#define MT_USER_SHIFT U(6)
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/* All other bits are reserved */
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/*
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@ -89,10 +94,20 @@ typedef enum {
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*/
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MT_EXECUTE = U(0) << MT_EXECUTE_SHIFT,
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MT_EXECUTE_NEVER = U(1) << MT_EXECUTE_SHIFT,
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/*
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* When mapping a region at EL0 or EL1, this attribute will be used to
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* determine if a User mapping (EL0) will be created or a Privileged
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* mapping (EL1).
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*/
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MT_USER = U(1) << MT_USER_SHIFT,
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MT_PRIVILEGED = U(0) << MT_USER_SHIFT,
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} mmap_attr_t;
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/* Compound attributes for most common usages */
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#define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE)
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#define MT_RO_DATA (MT_MEMORY | MT_RO | MT_EXECUTE_NEVER)
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#define MT_RW_DATA (MT_MEMORY | MT_RW | MT_EXECUTE_NEVER)
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/*
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* Structure for specifying a single region of memory.
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@ -149,8 +164,25 @@ typedef struct xlat_ctx xlat_ctx_t;
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*/
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#define REGISTER_XLAT_CONTEXT(_ctx_name, _mmap_count, _xlat_tables_count, \
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_virt_addr_space_size, _phy_addr_space_size) \
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_REGISTER_XLAT_CONTEXT(_ctx_name, _mmap_count, _xlat_tables_count, \
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_virt_addr_space_size, _phy_addr_space_size)
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_REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, _mmap_count, \
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_xlat_tables_count, \
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_virt_addr_space_size, \
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_phy_addr_space_size, \
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IMAGE_XLAT_DEFAULT_REGIME)
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/*
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* Same as REGISTER_XLAT_CONTEXT plus the additional parameter _xlat_regime to
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* specify the translation regime managed by this xlat_ctx_t instance. The
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* values are the one from xlat_regime_t enumeration.
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*/
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#define REGISTER_XLAT_CONTEXT2(_ctx_name, _mmap_count, _xlat_tables_count, \
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_virt_addr_space_size, _phy_addr_space_size, \
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_xlat_regime) \
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_REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, _mmap_count, \
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_xlat_tables_count, \
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_virt_addr_space_size, \
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_phy_addr_space_size, \
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_xlat_regime)
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/******************************************************************************
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* Generic translation table APIs.
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@ -99,11 +99,12 @@ struct xlat_ctx {
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unsigned int initialized;
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/*
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* Bit mask that has to be ORed to the rest of a translation table
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* descriptor in order to prohibit execution of code at the exception
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* level of this translation context.
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* Translation regime managed by this xlat_ctx_t. It takes the values of
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* the enumeration xlat_regime_t. The type is "int" to avoid a circular
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* dependency on xlat_tables_v2.h, but this member must be treated as
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* xlat_regime_t.
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*/
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uint64_t execute_never_mask;
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int xlat_regime;
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};
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#if PLAT_XLAT_TABLES_DYNAMIC
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@ -120,9 +121,9 @@ struct xlat_ctx {
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/* do nothing */
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#endif /* PLAT_XLAT_TABLES_DYNAMIC */
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#define _REGISTER_XLAT_CONTEXT(_ctx_name, _mmap_count, _xlat_tables_count, \
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_virt_addr_space_size, _phy_addr_space_size) \
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#define _REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, _mmap_count, _xlat_tables_count, \
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_virt_addr_space_size, _phy_addr_space_size, \
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_xlat_regime) \
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CASSERT(CHECK_VIRT_ADDR_SPACE_SIZE(_virt_addr_space_size), \
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assert_invalid_virtual_addr_space_size_for_##_ctx_name); \
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\
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@ -154,12 +155,23 @@ struct xlat_ctx {
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.tables = _ctx_name##_xlat_tables, \
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.tables_num = _xlat_tables_count, \
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_REGISTER_DYNMAP_STRUCT(_ctx_name) \
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.xlat_regime = (_xlat_regime), \
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.max_pa = 0, \
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.max_va = 0, \
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.next_table = 0, \
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.initialized = 0, \
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}
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/* This IMAGE_EL macro must not to be used outside the library */
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#if IMAGE_BL1 || IMAGE_BL31
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# define IMAGE_EL 3
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# define IMAGE_XLAT_DEFAULT_REGIME EL3_REGIME
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#else
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# define IMAGE_EL 1
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# define IMAGE_XLAT_DEFAULT_REGIME EL1_EL0_REGIME
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#endif
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#endif /*__ASSEMBLY__*/
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#endif /* __XLAT_TABLES_V2_HELPERS_H__ */
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@ -22,7 +22,7 @@ unsigned long long xlat_arch_get_max_supported_pa(void)
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}
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#endif /* ENABLE_ASSERTIONS*/
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int is_mmu_enabled(void)
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int is_mmu_enabled_ctx(const xlat_ctx_t *ctx __unused)
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{
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return (read_sctlr() & SCTLR_M_BIT) != 0;
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}
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@ -88,11 +88,6 @@ int xlat_arch_current_el(void)
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return 3;
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}
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uint64_t xlat_arch_get_xn_desc(int el __unused)
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{
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return UPPER_ATTRS(XN);
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}
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/*******************************************************************************
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* Function for enabling the MMU in Secure PL1, assuming that the page tables
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* have already been created.
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@ -0,0 +1,22 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __XLAT_TABLES_ARCH_PRIVATE_H__
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#define __XLAT_TABLES_ARCH_PRIVATE_H__
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#include <xlat_tables_defs.h>
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#include <xlat_tables_v2.h>
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/*
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* Return the execute-never mask that will prevent instruction fetch at the
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* given translation regime.
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*/
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static inline uint64_t xlat_arch_regime_get_xn_desc(xlat_regime_t regime __unused)
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{
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return UPPER_ATTRS(XN);
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}
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#endif /* __XLAT_TABLES_ARCH_PRIVATE_H__ */
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@ -16,12 +16,6 @@
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#include <xlat_tables_v2.h>
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#include "../xlat_tables_private.h"
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#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
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# define IMAGE_EL 3
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#else
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# define IMAGE_EL 1
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#endif
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static unsigned long long calc_physical_addr_size_bits(
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unsigned long long max_addr)
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{
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@ -70,17 +64,19 @@ unsigned long long xlat_arch_get_max_supported_pa(void)
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}
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#endif /* ENABLE_ASSERTIONS*/
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int is_mmu_enabled(void)
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int is_mmu_enabled_ctx(const xlat_ctx_t *ctx)
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{
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#if IMAGE_EL == 1
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assert(IS_IN_EL(1));
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return (read_sctlr_el1() & SCTLR_M_BIT) != 0;
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#elif IMAGE_EL == 3
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assert(IS_IN_EL(3));
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return (read_sctlr_el3() & SCTLR_M_BIT) != 0;
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#endif
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if (ctx->xlat_regime == EL1_EL0_REGIME) {
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assert(xlat_arch_current_el() >= 1);
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return (read_sctlr_el1() & SCTLR_M_BIT) != 0;
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} else {
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assert(ctx->xlat_regime == EL3_REGIME);
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assert(xlat_arch_current_el() >= 3);
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return (read_sctlr_el3() & SCTLR_M_BIT) != 0;
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}
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}
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void xlat_arch_tlbi_va(uintptr_t va)
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{
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#if IMAGE_EL == 1
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@ -149,16 +145,6 @@ int xlat_arch_current_el(void)
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return el;
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}
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uint64_t xlat_arch_get_xn_desc(int el)
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{
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if (el == 3) {
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return UPPER_ATTRS(XN);
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} else {
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assert(el == 1);
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return UPPER_ATTRS(PXN);
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}
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}
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/*******************************************************************************
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* Macro generating the code for the function enabling the MMU in the given
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* exception level, assuming that the pagetables have already been created.
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@ -0,0 +1,28 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __XLAT_TABLES_ARCH_PRIVATE_H__
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#define __XLAT_TABLES_ARCH_PRIVATE_H__
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#include <assert.h>
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#include <xlat_tables_defs.h>
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#include <xlat_tables_v2.h>
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/*
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* Return the execute-never mask that will prevent instruction fetch at all ELs
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* that are part of the given translation regime.
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*/
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static inline uint64_t xlat_arch_regime_get_xn_desc(xlat_regime_t regime)
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{
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if (regime == EL1_EL0_REGIME) {
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return UPPER_ATTRS(UXN) | UPPER_ATTRS(PXN);
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} else {
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assert(regime == EL3_REGIME);
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return UPPER_ATTRS(XN);
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}
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}
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#endif /* __XLAT_TABLES_ARCH_PRIVATE_H__ */
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@ -7,3 +7,5 @@
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XLAT_TABLES_LIB_SRCS := $(addprefix lib/xlat_tables_v2/, \
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${ARCH}/xlat_tables_arch.c \
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xlat_tables_internal.c)
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INCLUDES += -Ilib/xlat_tables_v2/${ARCH}
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@ -14,7 +14,7 @@
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#include <string.h>
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#include <types.h>
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#include <utils.h>
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#include <xlat_tables_arch.h>
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#include <xlat_tables_arch_private.h>
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#include <xlat_tables_defs.h>
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#include <xlat_tables_v2.h>
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@ -112,9 +112,11 @@ static uint64_t *xlat_table_get_empty(xlat_ctx_t *ctx)
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#endif /* PLAT_XLAT_TABLES_DYNAMIC */
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/* Returns a block/page table descriptor for the given level and attributes. */
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static uint64_t xlat_desc(mmap_attr_t attr, unsigned long long addr_pa,
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int level, uint64_t execute_never_mask)
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/*
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* Returns a block/page table descriptor for the given level and attributes.
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*/
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uint64_t xlat_desc(const xlat_ctx_t *ctx, mmap_attr_t attr,
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unsigned long long addr_pa, int level)
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{
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uint64_t desc;
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int mem_type;
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@ -133,9 +135,28 @@ static uint64_t xlat_desc(mmap_attr_t attr, unsigned long long addr_pa,
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* Deduce other fields of the descriptor based on the MT_NS and MT_RW
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* memory region attributes.
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*/
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desc |= LOWER_ATTRS(ACCESS_FLAG);
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desc |= (attr & MT_NS) ? LOWER_ATTRS(NS) : 0;
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desc |= (attr & MT_RW) ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO);
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desc |= LOWER_ATTRS(ACCESS_FLAG);
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/*
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* Do not allow unprivileged access when the mapping is for a privileged
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* EL. For translation regimes that do not have mappings for access for
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* lower exception levels, set AP[2] to AP_NO_ACCESS_UNPRIVILEGED.
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*/
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if (ctx->xlat_regime == EL1_EL0_REGIME) {
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if (attr & MT_USER) {
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/* EL0 mapping requested, so we give User access */
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desc |= LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED);
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} else {
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/* EL1 mapping requested, no User access granted */
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desc |= LOWER_ATTRS(AP_NO_ACCESS_UNPRIVILEGED);
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}
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} else {
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assert(ctx->xlat_regime == EL3_REGIME);
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desc |= LOWER_ATTRS(AP_NO_ACCESS_UNPRIVILEGED);
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}
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/*
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* Deduce shareability domain and executability of the memory region
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@ -156,7 +177,7 @@ static uint64_t xlat_desc(mmap_attr_t attr, unsigned long long addr_pa,
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* fetch, which could be an issue if this memory region
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* corresponds to a read-sensitive peripheral.
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*/
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desc |= execute_never_mask;
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desc |= xlat_arch_regime_get_xn_desc(ctx->xlat_regime);
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} else { /* Normal memory */
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/*
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@ -171,10 +192,13 @@ static uint64_t xlat_desc(mmap_attr_t attr, unsigned long long addr_pa,
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* translation table.
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*
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* For read-only memory, rely on the MT_EXECUTE/MT_EXECUTE_NEVER
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* attribute to figure out the value of the XN bit.
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* attribute to figure out the value of the XN bit. The actual
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* XN bit(s) to set in the descriptor depends on the context's
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* translation regime and the policy applied in
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* xlat_arch_regime_get_xn_desc().
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*/
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if ((attr & MT_RW) || (attr & MT_EXECUTE_NEVER)) {
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desc |= execute_never_mask;
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desc |= xlat_arch_regime_get_xn_desc(ctx->xlat_regime);
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}
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if (mem_type == MT_MEMORY) {
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@ -314,7 +338,7 @@ static void xlat_tables_unmap_region(xlat_ctx_t *ctx, mmap_region_t *mm,
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if (action == ACTION_WRITE_BLOCK_ENTRY) {
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table_base[table_idx] = INVALID_DESC;
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xlat_arch_tlbi_va(table_idx_va);
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xlat_arch_tlbi_va_regime(table_idx_va, ctx->xlat_regime);
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} else if (action == ACTION_RECURSE_INTO_TABLE) {
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@ -330,7 +354,8 @@ static void xlat_tables_unmap_region(xlat_ctx_t *ctx, mmap_region_t *mm,
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*/
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if (xlat_table_is_empty(ctx, subtable)) {
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table_base[table_idx] = INVALID_DESC;
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xlat_arch_tlbi_va(table_idx_va);
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xlat_arch_tlbi_va_regime(table_idx_va,
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ctx->xlat_regime);
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}
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} else {
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@ -536,8 +561,7 @@ static uintptr_t xlat_tables_map_region(xlat_ctx_t *ctx, mmap_region_t *mm,
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if (action == ACTION_WRITE_BLOCK_ENTRY) {
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table_base[table_idx] =
|
||||
xlat_desc(mm->attr, table_idx_pa, level,
|
||||
ctx->execute_never_mask);
|
||||
xlat_desc(ctx, mm->attr, table_idx_pa, level);
|
||||
|
||||
} else if (action == ACTION_CREATE_NEW_TABLE) {
|
||||
|
||||
|
|
@ -882,9 +906,8 @@ int mmap_add_dynamic_region_ctx(xlat_ctx_t *ctx, mmap_region_t *mm)
|
|||
.size = end_va - mm->base_va,
|
||||
.attr = 0
|
||||
};
|
||||
xlat_tables_unmap_region(ctx,
|
||||
&unmap_mm, 0, ctx->base_table,
|
||||
ctx->base_table_entries, ctx->base_level);
|
||||
xlat_tables_unmap_region(ctx, &unmap_mm, 0, ctx->base_table,
|
||||
ctx->base_table_entries, ctx->base_level);
|
||||
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
|
@ -999,9 +1022,10 @@ int mmap_remove_dynamic_region(uintptr_t base_va, size_t size)
|
|||
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
|
||||
|
||||
/* Print the attributes of the specified block descriptor. */
|
||||
static void xlat_desc_print(uint64_t desc, uint64_t execute_never_mask)
|
||||
static void xlat_desc_print(xlat_ctx_t *ctx, uint64_t desc)
|
||||
{
|
||||
int mem_type_index = ATTR_INDEX_GET(desc);
|
||||
xlat_regime_t xlat_regime = ctx->xlat_regime;
|
||||
|
||||
if (mem_type_index == ATTR_IWBWA_OWBWA_NTR_INDEX) {
|
||||
tf_printf("MEM");
|
||||
|
|
@ -1012,9 +1036,49 @@ static void xlat_desc_print(uint64_t desc, uint64_t execute_never_mask)
|
|||
tf_printf("DEV");
|
||||
}
|
||||
|
||||
tf_printf(LOWER_ATTRS(AP_RO) & desc ? "-RO" : "-RW");
|
||||
const char *priv_str = "(PRIV)";
|
||||
const char *user_str = "(USER)";
|
||||
|
||||
/*
|
||||
* Showing Privileged vs Unprivileged only makes sense for EL1&0
|
||||
* mappings
|
||||
*/
|
||||
const char *ro_str = "-RO";
|
||||
const char *rw_str = "-RW";
|
||||
const char *no_access_str = "-NOACCESS";
|
||||
|
||||
if (xlat_regime == EL3_REGIME) {
|
||||
/* For EL3, the AP[2] bit is all what matters */
|
||||
tf_printf((desc & LOWER_ATTRS(AP_RO)) ? ro_str : rw_str);
|
||||
} else {
|
||||
const char *ap_str = (desc & LOWER_ATTRS(AP_RO)) ? ro_str : rw_str;
|
||||
tf_printf(ap_str);
|
||||
tf_printf(priv_str);
|
||||
/*
|
||||
* EL0 can only have the same permissions as EL1 or no
|
||||
* permissions at all.
|
||||
*/
|
||||
tf_printf((desc & LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED))
|
||||
? ap_str : no_access_str);
|
||||
tf_printf(user_str);
|
||||
}
|
||||
|
||||
const char *xn_str = "-XN";
|
||||
const char *exec_str = "-EXEC";
|
||||
|
||||
if (xlat_regime == EL3_REGIME) {
|
||||
/* For EL3, the XN bit is all what matters */
|
||||
tf_printf(LOWER_ATTRS(XN) & desc ? xn_str : exec_str);
|
||||
} else {
|
||||
/* For EL0 and EL1, we need to know who has which rights */
|
||||
tf_printf(LOWER_ATTRS(PXN) & desc ? xn_str : exec_str);
|
||||
tf_printf(priv_str);
|
||||
|
||||
tf_printf(LOWER_ATTRS(UXN) & desc ? xn_str : exec_str);
|
||||
tf_printf(user_str);
|
||||
}
|
||||
|
||||
tf_printf(LOWER_ATTRS(NS) & desc ? "-NS" : "-S");
|
||||
tf_printf(execute_never_mask & desc ? "-XN" : "-EXEC");
|
||||
}
|
||||
|
||||
static const char * const level_spacers[] = {
|
||||
|
|
@ -1031,9 +1095,10 @@ static const char *invalid_descriptors_ommited =
|
|||
* Recursive function that reads the translation tables passed as an argument
|
||||
* and prints their status.
|
||||
*/
|
||||
static void xlat_tables_print_internal(const uintptr_t table_base_va,
|
||||
static void xlat_tables_print_internal(xlat_ctx_t *ctx,
|
||||
const uintptr_t table_base_va,
|
||||
uint64_t *const table_base, const int table_entries,
|
||||
const unsigned int level, const uint64_t execute_never_mask)
|
||||
const unsigned int level)
|
||||
{
|
||||
assert(level <= XLAT_TABLE_LEVEL_MAX);
|
||||
|
||||
|
|
@ -1092,17 +1157,16 @@ static void xlat_tables_print_internal(const uintptr_t table_base_va,
|
|||
|
||||
uintptr_t addr_inner = desc & TABLE_ADDR_MASK;
|
||||
|
||||
xlat_tables_print_internal(table_idx_va,
|
||||
xlat_tables_print_internal(ctx, table_idx_va,
|
||||
(uint64_t *)addr_inner,
|
||||
XLAT_TABLE_ENTRIES, level+1,
|
||||
execute_never_mask);
|
||||
XLAT_TABLE_ENTRIES, level + 1);
|
||||
} else {
|
||||
tf_printf("%sVA:%p PA:0x%llx size:0x%zx ",
|
||||
level_spacers[level],
|
||||
(void *)table_idx_va,
|
||||
(unsigned long long)(desc & TABLE_ADDR_MASK),
|
||||
level_size);
|
||||
xlat_desc_print(desc, execute_never_mask);
|
||||
xlat_desc_print(ctx, desc);
|
||||
tf_printf("\n");
|
||||
}
|
||||
}
|
||||
|
|
@ -1122,7 +1186,15 @@ static void xlat_tables_print_internal(const uintptr_t table_base_va,
|
|||
void xlat_tables_print(xlat_ctx_t *ctx)
|
||||
{
|
||||
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
|
||||
const char *xlat_regime_str;
|
||||
if (ctx->xlat_regime == EL1_EL0_REGIME) {
|
||||
xlat_regime_str = "1&0";
|
||||
} else {
|
||||
assert(ctx->xlat_regime == EL3_REGIME);
|
||||
xlat_regime_str = "3";
|
||||
}
|
||||
VERBOSE("Translation tables state:\n");
|
||||
VERBOSE(" Xlat regime: EL%s\n", xlat_regime_str);
|
||||
VERBOSE(" Max allowed PA: 0x%llx\n", ctx->pa_max_address);
|
||||
VERBOSE(" Max allowed VA: %p\n", (void *) ctx->va_max_address);
|
||||
VERBOSE(" Max mapped PA: 0x%llx\n", ctx->max_pa);
|
||||
|
|
@ -1146,23 +1218,22 @@ void xlat_tables_print(xlat_ctx_t *ctx)
|
|||
used_page_tables, ctx->tables_num,
|
||||
ctx->tables_num - used_page_tables);
|
||||
|
||||
xlat_tables_print_internal(0, ctx->base_table, ctx->base_table_entries,
|
||||
ctx->base_level, ctx->execute_never_mask);
|
||||
xlat_tables_print_internal(ctx, 0, ctx->base_table,
|
||||
ctx->base_table_entries, ctx->base_level);
|
||||
#endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
|
||||
}
|
||||
|
||||
void init_xlat_tables_ctx(xlat_ctx_t *ctx)
|
||||
{
|
||||
assert(ctx != NULL);
|
||||
assert(!ctx->initialized);
|
||||
assert(ctx->xlat_regime == EL3_REGIME || ctx->xlat_regime == EL1_EL0_REGIME);
|
||||
assert(!is_mmu_enabled_ctx(ctx));
|
||||
|
||||
mmap_region_t *mm = ctx->mmap;
|
||||
|
||||
assert(!is_mmu_enabled());
|
||||
assert(!ctx->initialized);
|
||||
|
||||
print_mmap(mm);
|
||||
|
||||
ctx->execute_never_mask =
|
||||
xlat_arch_get_xn_desc(xlat_arch_current_el());
|
||||
|
||||
/* All tables must be zeroed before mapping any region. */
|
||||
|
||||
for (unsigned int i = 0; i < ctx->base_table_entries; i++)
|
||||
|
|
|
|||
|
|
@ -75,13 +75,6 @@ void xlat_tables_print(xlat_ctx_t *ctx);
|
|||
/* Returns the current Exception Level. The returned EL must be 1 or higher. */
|
||||
int xlat_arch_current_el(void);
|
||||
|
||||
/*
|
||||
* Returns the bit mask that has to be ORed to the rest of a translation table
|
||||
* descriptor so that execution of code is prohibited at the given Exception
|
||||
* Level.
|
||||
*/
|
||||
uint64_t xlat_arch_get_xn_desc(int el);
|
||||
|
||||
/*
|
||||
* Return the maximum physical address supported by the hardware.
|
||||
* This value depends on the execution state (AArch32/AArch64).
|
||||
|
|
@ -92,7 +85,10 @@ unsigned long long xlat_arch_get_max_supported_pa(void);
|
|||
void enable_mmu_arch(unsigned int flags, uint64_t *base_table,
|
||||
unsigned long long pa, uintptr_t max_va);
|
||||
|
||||
/* Return 1 if the MMU of this Exception Level is enabled, 0 otherwise. */
|
||||
int is_mmu_enabled(void);
|
||||
/*
|
||||
* Return 1 if the MMU of the translation regime managed by the given xlat_ctx_t
|
||||
* is enabled, 0 otherwise.
|
||||
*/
|
||||
int is_mmu_enabled_ctx(const xlat_ctx_t *ctx);
|
||||
|
||||
#endif /* __XLAT_TABLES_PRIVATE_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue