feat(plat/imx8m): add system_reset2 implementation
Add imx_system_reset2 which extends existing SYSTEM_RESET. It provides architectural reset definitions and vendor-specific resets. By default warm reset is triggered. Also refactor existing implementation of wdog reset, add details about each flag used. Change-Id: Ia7348c32c385f1c61f8085776e81dd1e38ddda5c Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
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@ -152,19 +152,45 @@ void imx_get_sys_suspend_power_state(psci_power_state_t *req_state)
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req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE;
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}
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void __dead2 imx_system_reset(void)
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static void __dead2 imx_wdog_restart(bool external_reset)
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{
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uintptr_t wdog_base = IMX_WDOG_BASE;
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unsigned int val;
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/* WDOG_B reset */
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val = mmio_read_16(wdog_base);
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#ifdef IMX_WDOG_B_RESET
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val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_WDE |
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WDOG_WCR_WDT | WDOG_WCR_SRS;
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#else
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val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_SRS;
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#endif
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/*
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* Common watchdog init flags, for additional details check
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* 6.6.4.1 Watchdog Control Register (WDOGx_WCR)
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*
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* Initial bit selection:
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* WDOG_WCR_WDE - Enable the watchdog.
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*
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* 0x000E mask is used to keep previous values (that could be set
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* in SPL) of WDBG and WDE/WDT (both are write-one once-only bits).
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*/
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val = (val & 0x000E) | WDOG_WCR_WDE;
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if (external_reset) {
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/*
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* To assert WDOG_B (external reset) we have
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* to set WDA bit 0 (already set in previous step).
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* SRS bits are required to be set to 1 (no effect on the
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* system).
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*/
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val |= WDOG_WCR_SRS;
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} else {
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/*
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* To assert Software Reset Signal (internal reset) we have
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* to set SRS bit to 0 (already set in previous step).
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* SRE bit is required to be set to 1 when used in
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* conjunction with the Software Reset Signal before
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* SRS asserton, otherwise SRS bit will just automatically
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* reset to 1.
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*
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* Also we set WDA to 1 (no effect on system).
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*/
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val |= WDOG_WCR_SRE | WDOG_WCR_WDA;
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}
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mmio_write_16(wdog_base, val);
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mmio_write_16(wdog_base + WDOG_WSR, 0x5555);
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@ -173,6 +199,27 @@ void __dead2 imx_system_reset(void)
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;
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}
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void __dead2 imx_system_reset(void)
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{
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#ifdef IMX_WDOG_B_RESET
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imx_wdog_restart(true);
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#else
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imx_wdog_restart(false);
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#endif
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}
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int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
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{
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imx_wdog_restart(false);
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/*
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* imx_wdog_restart cannot return (as it's a __dead function),
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* however imx_system_reset2 has to return some value according
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* to PSCI v1.1 spec.
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*/
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return 0;
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}
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void __dead2 imx_system_off(void)
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{
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mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, SNVS_LPCR_SRTC_ENV |
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@ -28,6 +28,7 @@ static const plat_psci_ops_t imx_plat_psci_ops = {
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.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
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.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
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.system_reset = imx_system_reset,
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.system_reset2 = imx_system_reset2,
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.system_off = imx_system_off,
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};
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@ -117,6 +117,7 @@ static const plat_psci_ops_t imx_plat_psci_ops = {
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.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
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.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
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.system_reset = imx_system_reset,
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.system_reset2 = imx_system_reset2,
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.system_off = imx_system_off,
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};
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@ -19,5 +19,6 @@ void imx_cpu_standby(plat_local_state_t cpu_state);
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void imx_domain_suspend(const psci_power_state_t *target_state);
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void imx_domain_suspend_finish(const psci_power_state_t *target_state);
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void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state);
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int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie);
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#endif /* IMX8M_PSCI_H */
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