From 8e1cc44900d31dd60ad6c5e3853f9df6ea9826e9 Mon Sep 17 00:00:00 2001 From: Chandni Cherukuri Date: Thu, 2 Aug 2018 12:29:07 +0530 Subject: [PATCH 1/2] sgi: disable CPU power down bit in reset handler On SGI platforms, the 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an explicit write to clear it for hotplug and idle to function correctly. The reset value of this bit is zero but it still requires this explicit clear to zero. This indicates that this could be a model related issue but for now this issue can be fixed be clearing the CORE_PWRDN_EN in the platform specific reset handler function. Change-Id: I4222930daa9a3abacdace6b7c3f4a5472ac0cb19 Signed-off-by: Chandni Cherukuri --- plat/arm/css/sgi/aarch64/sgi_helper.S | 40 +++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/plat/arm/css/sgi/aarch64/sgi_helper.S b/plat/arm/css/sgi/aarch64/sgi_helper.S index aaa51560f..d6f63ede9 100644 --- a/plat/arm/css/sgi/aarch64/sgi_helper.S +++ b/plat/arm/css/sgi/aarch64/sgi_helper.S @@ -7,9 +7,11 @@ #include #include #include +#include .globl plat_is_my_cpu_primary .globl plat_arm_calc_core_pos + .globl plat_reset_handler /* ----------------------------------------------------- * unsigned int plat_is_my_cpu_primary (void); @@ -65,3 +67,41 @@ func plat_arm_calc_core_pos madd x0, x1, x5, x0 ret endfunc plat_arm_calc_core_pos + + /* ------------------------------------------------------ + * Helper macro that reads the part number of the current + * CPU and jumps to the given label if it matches the CPU + * MIDR provided. + * + * Clobbers x0. + * ----------------------------------------------------- + */ + .macro jump_if_cpu_midr _cpu_midr, _label + mrs x0, midr_el1 + ubfx x0, x0, MIDR_PN_SHIFT, #12 + cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) + b.eq \_label + .endm + + /* ----------------------------------------------------- + * void plat_reset_handler(void); + * + * Determine the CPU MIDR and disable power down bit for + * that CPU. + * ----------------------------------------------------- + */ +func plat_reset_handler + jump_if_cpu_midr CORTEX_A75_MIDR, A75 + ret + + /* ----------------------------------------------------- + * Disable CPU power down bit in power control register + * ----------------------------------------------------- + */ +A75: + mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 + bic x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK + msr CORTEX_A75_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc plat_reset_handler From a41d1b2ce35d4bee558d48a677a19bd0b9885b1f Mon Sep 17 00:00:00 2001 From: Chandni Cherukuri Date: Wed, 1 Aug 2018 15:58:48 +0530 Subject: [PATCH 2/2] plat/sgi: switch to using scmi The Arm SGI platforms can switch to using SCMI. So enable support for SCMI and remove portions of code that would be unused after switching to SCMI. Change-Id: Ifd9e1c944745f703da5f970b5daf1be2b07ed14e Signed-off-by: Chandni Cherukuri --- plat/arm/css/sgi/aarch64/sgi_helper.S | 20 -------------------- plat/arm/css/sgi/include/platform_def.h | 5 ----- plat/arm/css/sgi/sgi-common.mk | 2 ++ plat/arm/css/sgi/sgi_topology.c | 9 +++++++++ 4 files changed, 11 insertions(+), 25 deletions(-) diff --git a/plat/arm/css/sgi/aarch64/sgi_helper.S b/plat/arm/css/sgi/aarch64/sgi_helper.S index d6f63ede9..dd0fc5bbd 100644 --- a/plat/arm/css/sgi/aarch64/sgi_helper.S +++ b/plat/arm/css/sgi/aarch64/sgi_helper.S @@ -9,29 +9,9 @@ #include #include - .globl plat_is_my_cpu_primary .globl plat_arm_calc_core_pos .globl plat_reset_handler - /* ----------------------------------------------------- - * unsigned int plat_is_my_cpu_primary (void); - * - * Find out whether the current cpu is the primary - * cpu (applicable only after a cold boot) - * ----------------------------------------------------- - */ -func plat_is_my_cpu_primary - mov x9, x30 - bl plat_my_core_pos - ldr x1, =SGI_BOOT_CFG_ADDR - ldr x1, [x1] - ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \ - #PLAT_CSS_PRIMARY_CPU_BIT_WIDTH - cmp x0, x1 - cset w0, eq - ret x9 -endfunc plat_is_my_cpu_primary - /* ----------------------------------------------------- * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) * diff --git a/plat/arm/css/sgi/include/platform_def.h b/plat/arm/css/sgi/include/platform_def.h index 169ae1b75..c645d109e 100644 --- a/plat/arm/css/sgi/include/platform_def.h +++ b/plat/arm/css/sgi/include/platform_def.h @@ -77,11 +77,6 @@ CSS_SGI_DEVICE_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 -#define SGI_BOOT_CFG_ADDR 0x45410000 -#define PLAT_CSS_PRIMARY_CPU_SHIFT 8 -#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 6 - /* GIC related constants */ #define PLAT_ARM_GICD_BASE 0x30000000 #define PLAT_ARM_GICC_BASE 0x2C000000 diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk index e0996c78d..74d255cba 100644 --- a/plat/arm/css/sgi/sgi-common.mk +++ b/plat/arm/css/sgi/sgi-common.mk @@ -4,6 +4,8 @@ # SPDX-License-Identifier: BSD-3-Clause # +CSS_USE_SCMI_SDS_DRIVER := 1 + ENABLE_PLAT_COMPAT := 0 CSS_ENT_BASE := plat/arm/css/sgi diff --git a/plat/arm/css/sgi/sgi_topology.c b/plat/arm/css/sgi/sgi_topology.c index 1d2e027df..3f6357bd1 100644 --- a/plat/arm/css/sgi/sgi_topology.c +++ b/plat/arm/css/sgi/sgi_topology.c @@ -42,3 +42,12 @@ unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) { return sgi_topology.plat_cluster_core_count; } + +/******************************************************************************* + * The array mapping platform core position (implemented by plat_my_core_pos()) + * to the SCMI power domain ID implemented by SCP. + ******************************************************************************/ +const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[32] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 +};