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Migrate FVP port to use common code 

Major update to the FVP platform port to use the common platform code
in (include/)plat/arm/* and (include/)plat/common/*. This mainly
consists of removing duplicated code but also introduces some small
behavioural changes where there was unnecessary variation between the
FVP and Juno ports. See earlier commit titled `Add common ARM and CSS
platform code` for details.

Also add support for Foundation FVP version 9.1 during FVP config
setup to prevent a warning being emitted in the console.

Change-Id: I254ca854987642ce09d1b924c9fd410a6e13e3bc
This commit is contained in:
Dan Handley 2015-03-19 19:17:53 +00:00
parent b4315306ad
commit 60eea55e37
21 changed files with 331 additions and 2159 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

78
include/plat/common/plat_config.h
View File

@ -1,78 +0,0 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLAT_CONFIG_H__
#define __PLAT_CONFIG_H__
#define CONFIG_GICC_BASE_OFFSET 0x4
#ifndef __ASSEMBLY__
#include <cassert.h>
enum plat_config_flags {
/* Whether Base FVP memory map is in use */
CONFIG_BASE_MMAP = 0x1,
/* Whether CCI should be enabled */
CONFIG_HAS_CCI = 0x2,
/* Whether TZC should be configured */
CONFIG_HAS_TZC = 0x4
};
typedef struct plat_config {
unsigned int gicd_base;
unsigned int gicc_base;
unsigned int gich_base;
unsigned int gicv_base;
unsigned int max_aff0;
unsigned int max_aff1;
unsigned long flags;
} plat_config_t;
inline const plat_config_t *get_plat_config();
CASSERT(CONFIG_GICC_BASE_OFFSET == __builtin_offsetof(
plat_config_t, gicc_base),
assert_gicc_base_offset_mismatch);
/* If used, plat_config must be defined and populated in the platform port*/
extern plat_config_t plat_config;
inline const plat_config_t *get_plat_config()
{
return &plat_config;
}
#endif /* __ASSEMBLY__ */
#endif /* __PLAT_CONFIG_H__ */

284
plat/fvp/aarch64/fvp_common.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -28,35 +28,24 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <arch_helpers.h>
#include <arm_config.h>
#include <arm_def.h>
#include <arm_gic.h>
#include <bl_common.h>
#include <cci.h>
#include <debug.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
#include <plat_config.h>
#include <xlat_tables.h>
#include <plat_arm.h>
#include <v2m_def.h>
#include "../fvp_def.h"
/*******************************************************************************
* plat_config holds the characteristics of the differences between the three
* FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold
* boot at each boot stage by the primary before enabling the MMU (to allow cci
* arm_config holds the characteristics of the differences between the three FVP
* platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
* at each boot stage by the primary before enabling the MMU (to allow cci
* configuration) & used thereafter. Each BL will have its own copy to allow
* independent operation.
******************************************************************************/
plat_config_t plat_config;
#define MAP_SHARED_RAM MAP_REGION_FLAT(FVP_SHARED_MEM_BASE, \
FVP_SHARED_MEM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
#define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
FLASH0_SIZE, \
MT_MEMORY | MT_RO | MT_SECURE)
arm_config_t arm_config;
#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
DEVICE0_SIZE, \
@ -66,122 +55,79 @@ plat_config_t plat_config;
DEVICE1_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
DRAM1_NS_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
#define MAP_TSP_SEC_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
TSP_SEC_MEM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
/*
* Table of regions for various BL stages to map using the MMU.
* This doesn't include TZRAM as the 'mem_layout' argument passed to
* configure_mmu_elx() will give the available subset of that,
* arm_configure_mmu_elx() will give the available subset of that,
*/
#if IMAGE_BL1
const mmap_region_t fvp_mmap[] = {
MAP_SHARED_RAM,
MAP_FLASH0,
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_FLASH0,
V2M_MAP_IOFPGA,
MAP_DEVICE0,
MAP_DEVICE1,
{0}
};
#endif
#if IMAGE_BL2
const mmap_region_t fvp_mmap[] = {
MAP_SHARED_RAM,
MAP_FLASH0,
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_FLASH0,
V2M_MAP_IOFPGA,
MAP_DEVICE0,
MAP_DEVICE1,
MAP_DRAM1_NS,
MAP_TSP_SEC_MEM,
ARM_MAP_NS_DRAM1,
ARM_MAP_TSP_SEC_MEM,
{0}
};
#endif
#if IMAGE_BL31
const mmap_region_t fvp_mmap[] = {
MAP_SHARED_RAM,
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_IOFPGA,
MAP_DEVICE0,
MAP_DEVICE1,
{0}
};
#endif
#if IMAGE_BL32
const mmap_region_t fvp_mmap[] = {
const mmap_region_t plat_arm_mmap[] = {
V2M_MAP_IOFPGA,
MAP_DEVICE0,
MAP_DEVICE1,
{0}
};
#endif
CASSERT(ARRAY_SIZE(fvp_mmap) + FVP_BL_REGIONS \
<= MAX_MMAP_REGIONS, assert_max_mmap_regions);
ARM_CASSERT_MMAP
#if IMAGE_BL31 || IMAGE_BL32
/* Array of secure interrupts to be configured by the gic driver */
const unsigned int irq_sec_array[] = {
IRQ_TZ_WDOG,
IRQ_SEC_PHY_TIMER,
IRQ_SEC_SGI_0,
IRQ_SEC_SGI_1,
IRQ_SEC_SGI_2,
IRQ_SEC_SGI_3,
IRQ_SEC_SGI_4,
IRQ_SEC_SGI_5,
IRQ_SEC_SGI_6,
IRQ_SEC_SGI_7
ARM_IRQ_SEC_PHY_TIMER,
ARM_IRQ_SEC_SGI_0,
ARM_IRQ_SEC_SGI_1,
ARM_IRQ_SEC_SGI_2,
ARM_IRQ_SEC_SGI_3,
ARM_IRQ_SEC_SGI_4,
ARM_IRQ_SEC_SGI_5,
ARM_IRQ_SEC_SGI_6,
ARM_IRQ_SEC_SGI_7
};
/*******************************************************************************
* Macro generating the code for the function setting up the pagetables as per
* the platform memory map & initialize the mmu, for the given exception level
******************************************************************************/
#if USE_COHERENT_MEM
#define DEFINE_CONFIGURE_MMU_EL(_el) \
void fvp_configure_mmu_el##_el(unsigned long total_base, \
unsigned long total_size, \
unsigned long ro_start, \
unsigned long ro_limit, \
unsigned long coh_start, \
unsigned long coh_limit) \
{ \
mmap_add_region(total_base, total_base, \
total_size, \
MT_MEMORY | MT_RW | MT_SECURE); \
mmap_add_region(ro_start, ro_start, \
ro_limit - ro_start, \
MT_MEMORY | MT_RO | MT_SECURE); \
mmap_add_region(coh_start, coh_start, \
coh_limit - coh_start, \
MT_DEVICE | MT_RW | MT_SECURE); \
mmap_add(fvp_mmap); \
init_xlat_tables(); \
\
enable_mmu_el##_el(0); \
}
#else
#define DEFINE_CONFIGURE_MMU_EL(_el) \
void fvp_configure_mmu_el##_el(unsigned long total_base, \
unsigned long total_size, \
unsigned long ro_start, \
unsigned long ro_limit) \
{ \
mmap_add_region(total_base, total_base, \
total_size, \
MT_MEMORY | MT_RW | MT_SECURE); \
mmap_add_region(ro_start, ro_start, \
ro_limit - ro_start, \
MT_MEMORY | MT_RO | MT_SECURE); \
mmap_add(fvp_mmap); \
init_xlat_tables(); \
\
enable_mmu_el##_el(0); \
}
#endif
void plat_arm_gic_init(void)
{
arm_gic_init(arm_config.gicc_base,
arm_config.gicd_base,
BASE_GICR_BASE,
irq_sec_array,
ARRAY_SIZE(irq_sec_array));
}
/* Define EL1 and EL3 variants of the function initialising the MMU */
DEFINE_CONFIGURE_MMU_EL(1)
DEFINE_CONFIGURE_MMU_EL(3)
#endif
/*******************************************************************************
* A single boot loader stack is expected to work on both the Foundation FVP
@ -190,15 +136,15 @@ DEFINE_CONFIGURE_MMU_EL(3)
* these platforms. This information is stored in a per-BL array to allow the
* code to take the correct path.Per BL platform configuration.
******************************************************************************/
int fvp_config_setup(void)
void fvp_config_setup(void)
{
unsigned int rev, hbi, bld, arch, sys_id;
sys_id = mmio_read_32(VE_SYSREGS_BASE + V2M_SYS_ID);
rev = (sys_id >> SYS_ID_REV_SHIFT) & SYS_ID_REV_MASK;
hbi = (sys_id >> SYS_ID_HBI_SHIFT) & SYS_ID_HBI_MASK;
bld = (sys_id >> SYS_ID_BLD_SHIFT) & SYS_ID_BLD_MASK;
arch = (sys_id >> SYS_ID_ARCH_SHIFT) & SYS_ID_ARCH_MASK;
sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
if (arch != ARCH_MODEL) {
ERROR("This firmware is for FVP models\n");
@ -211,16 +157,16 @@ int fvp_config_setup(void)
*/
switch (bld) {
case BLD_GIC_VE_MMAP:
plat_config.gicd_base = VE_GICD_BASE;
plat_config.gicc_base = VE_GICC_BASE;
plat_config.gich_base = VE_GICH_BASE;
plat_config.gicv_base = VE_GICV_BASE;
arm_config.gicd_base = VE_GICD_BASE;
arm_config.gicc_base = VE_GICC_BASE;
arm_config.gich_base = VE_GICH_BASE;
arm_config.gicv_base = VE_GICV_BASE;
break;
case BLD_GIC_A53A57_MMAP:
plat_config.gicd_base = BASE_GICD_BASE;
plat_config.gicc_base = BASE_GICC_BASE;
plat_config.gich_base = BASE_GICH_BASE;
plat_config.gicv_base = BASE_GICV_BASE;
arm_config.gicd_base = BASE_GICD_BASE;
arm_config.gicc_base = BASE_GICC_BASE;
arm_config.gich_base = BASE_GICH_BASE;
arm_config.gicv_base = BASE_GICV_BASE;
break;
default:
ERROR("Unsupported board build %x\n", bld);
@ -232,36 +178,37 @@ int fvp_config_setup(void)
* for the Foundation FVP.
*/
switch (hbi) {
case HBI_FOUNDATION:
plat_config.max_aff0 = 4;
plat_config.max_aff1 = 1;
plat_config.flags = 0;
case HBI_FOUNDATION_FVP:
arm_config.max_aff0 = 4;
arm_config.max_aff1 = 1;
arm_config.flags = 0;
/*
* Check for supported revisions of Foundation FVP
* Allow future revisions to run but emit warning diagnostic
*/
switch (rev) {
case REV_FOUNDATION_V2_0:
case REV_FOUNDATION_V2_1:
case REV_FOUNDATION_FVP_V2_0:
case REV_FOUNDATION_FVP_V2_1:
case REV_FOUNDATION_FVP_v9_1:
break;
default:
WARN("Unrecognized Foundation FVP revision %x\n", rev);
break;
}
break;
case HBI_FVP_BASE:
plat_config.max_aff0 = 4;
plat_config.max_aff1 = 2;
plat_config.flags |= CONFIG_BASE_MMAP | CONFIG_HAS_CCI |
CONFIG_HAS_TZC;
case HBI_BASE_FVP:
arm_config.max_aff0 = 4;
arm_config.max_aff1 = 2;
arm_config.flags |= ARM_CONFIG_BASE_MMAP |
ARM_CONFIG_HAS_CCI | ARM_CONFIG_HAS_TZC;
/*
* Check for supported revisions
* Allow future revisions to run but emit warning diagnostic
*/
switch (rev) {
case REV_FVP_BASE_V0:
case REV_BASE_FVP_V0:
break;
default:
WARN("Unrecognized Base FVP revision %x\n", rev);
@ -272,103 +219,26 @@ int fvp_config_setup(void)
ERROR("Unsupported board HBI number 0x%x\n", hbi);
panic();
}
return 0;
}
unsigned long plat_get_ns_image_entrypoint(void)
{
return NS_IMAGE_OFFSET;
}
uint64_t plat_get_syscnt_freq(void)
{
uint64_t counter_base_frequency;
/* Read the frequency from Frequency modes table */
counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
/* The first entry of the frequency modes table must not be 0 */
if (counter_base_frequency == 0)
panic();
return counter_base_frequency;
}
/* Map of CCI masters with the slave interfaces they are connected */
static const int cci_map[] = {
CCI400_CLUSTER0_SL_IFACE_IX,
CCI400_CLUSTER1_SL_IFACE_IX
};
void fvp_cci_init(void)
{
/*
* Initialize CCI-400 driver
*/
if (plat_config.flags & CONFIG_HAS_CCI)
cci_init(CCI400_BASE,
cci_map,
ARRAY_SIZE(cci_map));
if (arm_config.flags & ARM_CONFIG_HAS_CCI)
arm_cci_init();
}
void fvp_cci_enable(void)
{
if (plat_config.flags & CONFIG_HAS_CCI)
if (arm_config.flags & ARM_CONFIG_HAS_CCI)
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
}
void fvp_cci_disable(void)
{
if (plat_config.flags & CONFIG_HAS_CCI)
if (arm_config.flags & ARM_CONFIG_HAS_CCI)
cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
}
void fvp_gic_init(void)
{
arm_gic_init(plat_config.gicc_base,
plat_config.gicd_base,
BASE_GICR_BASE,
irq_sec_array,
ARRAY_SIZE(irq_sec_array));
}
/*******************************************************************************
* Gets SPSR for BL32 entry
******************************************************************************/
uint32_t fvp_get_spsr_for_bl32_entry(void)
{
/*
* The Secure Payload Dispatcher service is responsible for
* setting the SPSR prior to entry into the BL32 image.
*/
return 0;
}
/*******************************************************************************
* Gets SPSR for BL33 entry
******************************************************************************/
uint32_t fvp_get_spsr_for_bl33_entry(void)
{
unsigned long el_status;
unsigned int mode;
uint32_t spsr;
/* Figure out what mode we enter the non-secure world in */
el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
el_status &= ID_AA64PFR0_ELX_MASK;
if (el_status)
mode = MODE_EL2;
else
mode = MODE_EL1;
/*
* TODO: Consider the possibility of specifying the SPSR in
* the FIP ToC and allowing the platform to have a say as
* well.
*/
spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
return spsr;
}

67
plat/fvp/aarch64/fvp_helpers.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,24 +30,21 @@
#include <arch.h>
#include <asm_macros.S>
#include <bl_common.h>
#include <gic_v2.h>
#include <platform_def.h>
#include <pl011.h>
#include <v2m_def.h>
#include "../drivers/pwrc/fvp_pwrc.h"
#include "../fvp_def.h"
.globl platform_get_entrypoint
.globl plat_secondary_cold_boot_setup
.globl platform_get_entrypoint
.globl platform_mem_init
.globl plat_report_exception
.globl platform_is_primary_cpu
.globl plat_crash_console_init
.globl plat_crash_console_putc
.macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res
ldr \x_tmp, =VE_SYSREGS_BASE + V2M_SYS_ID
ldr \x_tmp, =V2M_SYSREGS_BASE + V2M_SYS_ID
ldr \w_tmp, [\x_tmp]
ubfx \w_tmp, \w_tmp, #SYS_ID_BLD_SHIFT, #SYS_ID_BLD_LENGTH
ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH
cmp \w_tmp, #BLD_GIC_VE_MMAP
csel \res, \param1, \param2, eq
.endm
@ -143,7 +140,7 @@ warm_reset:
*/
ldr x10, =MBOX_BASE
bl platform_get_core_pos
lsl x0, x0, #CACHE_WRITEBACK_SHIFT
lsl x0, x0, #ARM_CACHE_WRITEBACK_SHIFT
ldr x0, [x10, x0]
cbz x0, _panic
exit:
@ -174,27 +171,6 @@ loop:
ret
endfunc platform_mem_init
/* ---------------------------------------------
* void plat_report_exception(unsigned int type)
* Function to report an unhandled exception
* with platform-specific means.
* On FVP platform, it updates the LEDs
* to indicate where we are
* ---------------------------------------------
*/
func plat_report_exception
mrs x1, CurrentEl
lsr x1, x1, #MODE_EL_SHIFT
lsl x1, x1, #SYS_LED_EL_SHIFT
lsl x0, x0, #SYS_LED_EC_SHIFT
mov x2, #(SECURE << SYS_LED_SS_SHIFT)
orr x0, x0, x2
orr x0, x0, x1
mov x1, #VE_SYSREGS_BASE
add x1, x1, #V2M_SYS_LED
str w0, [x1]
ret
endfunc plat_report_exception
func platform_is_primary_cpu
and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
@ -202,32 +178,3 @@ func platform_is_primary_cpu
cset x0, eq
ret
endfunc platform_is_primary_cpu
/* Define a crash console for the plaform */
#define FVP_CRASH_CONSOLE_BASE PL011_UART1_BASE
/* ---------------------------------------------
* int plat_crash_console_init(void)
* Function to initialize the crash console
* without a C Runtime to print crash report.
* Clobber list : x0, x1, x2
* ---------------------------------------------
*/
func plat_crash_console_init
mov_imm x0, FVP_CRASH_CONSOLE_BASE
mov_imm x1, PL011_UART1_CLK_IN_HZ
mov_imm x2, PL011_BAUDRATE
b console_core_init
endfunc plat_crash_console_init
/* ---------------------------------------------
* int plat_crash_console_putc(int c)
* Function to print a character on the crash
* console without a C Runtime.
* Clobber list : x1, x2
* ---------------------------------------------
*/
func plat_crash_console_putc
mov_imm x1, FVP_CRASH_CONSOLE_BASE
b console_core_putc
endfunc plat_crash_console_putc

107
plat/fvp/bl1_fvp_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -28,114 +28,27 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
#include <console.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
#include "../../bl1/bl1_private.h"
#include "fvp_def.h"
#include <plat_arm.h>
#include "fvp_private.h"
#if USE_COHERENT_MEM
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
/* Data structure which holds the extents of the trusted SRAM for BL1*/
static meminfo_t bl1_tzram_layout;
meminfo_t *bl1_plat_sec_mem_layout(void)
{
return &bl1_tzram_layout;
}
/*******************************************************************************
* Perform any BL1 specific platform actions.
******************************************************************************/
void bl1_early_platform_setup(void)
{
const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
/* Initialize the console to provide early debug support */
console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = FVP_TRUSTED_SRAM_BASE;
bl1_tzram_layout.total_size = FVP_TRUSTED_SRAM_SIZE;
/* Calculate how much RAM BL1 is using and how much remains free */
bl1_tzram_layout.free_base = FVP_TRUSTED_SRAM_BASE;
bl1_tzram_layout.free_size = FVP_TRUSTED_SRAM_SIZE;
reserve_mem(&bl1_tzram_layout.free_base,
&bl1_tzram_layout.free_size,
BL1_RAM_BASE,
bl1_size);
arm_bl1_early_platform_setup();
/* Initialize the platform config for future decision making */
fvp_config_setup();
}
/*******************************************************************************
* Function which will evaluate how much of the trusted ram has been gobbled
* up by BL1 and return the base and size of whats available for loading BL2.
* Its called after coherency and the MMU have been turned on.
******************************************************************************/
void bl1_platform_setup(void)
{
/* Initialise the IO layer and register platform IO devices */
fvp_io_setup();
}
/*******************************************************************************
* Perform the very early platform specific architecture setup here. At the
* moment this only does basic initialization. Later architectural setup
* (bl1_arch_setup()) does not do anything platform specific.
******************************************************************************/
void bl1_plat_arch_setup(void)
{
/*
* Initialize CCI for this cluster during cold boot.
* No need for locks as no other CPU is active.
*/
fvp_cci_init();
/*
* Enable CCI coherency for the primary CPU's cluster.
*/
fvp_cci_enable();
fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
BL1_RO_BASE,
BL1_RO_LIMIT
#if USE_COHERENT_MEM
, BL1_COHERENT_RAM_BASE,
BL1_COHERENT_RAM_LIMIT
#endif
);
}
/*******************************************************************************
* Before calling this function BL2 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL2 and set SPSR and security state.
* On FVP we are only setting the security state, entrypoint
******************************************************************************/
void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image,
entry_point_info_t *bl2_ep)
{
SET_SECURITY_STATE(bl2_ep->h.attr, SECURE);
bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
}

256
plat/fvp/bl2_fvp_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -28,264 +28,14 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <platform.h>
#include <platform_def.h>
#include <string.h>
#include "fvp_def.h"
#include <plat_arm.h>
#include "fvp_private.h"
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
extern unsigned long __RO_START__;
extern unsigned long __RO_END__;
#if USE_COHERENT_MEM
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
#endif
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
*/
#define BL2_RO_BASE (unsigned long)(&__RO_START__)
#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout
__attribute__ ((aligned(CACHE_WRITEBACK_GRANULE)));
/* Assert that BL3-1 parameters fit in shared memory */
CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t)) <
(FVP_SHARED_MEM_BASE + FVP_SHARED_MEM_SIZE),
assert_bl31_params_do_not_fit_in_shared_memory);
/*******************************************************************************
* Reference to structures which holds the arguments which need to be passed
* to BL31
******************************************************************************/
static bl31_params_t *bl2_to_bl31_params;
static entry_point_info_t *bl31_ep_info;
meminfo_t *bl2_plat_sec_mem_layout(void)
{
return &bl2_tzram_layout;
}
/*******************************************************************************
* This function assigns a pointer to the memory that the platform has kept
* aside to pass platform specific and trusted firmware related information
* to BL31. This memory is allocated by allocating memory to
* bl2_to_bl31_params_mem_t structure which is a superset of all the
* structure whose information is passed to BL31
* NOTE: This function should be called only once and should be done
* before generating params to BL31
******************************************************************************/
bl31_params_t *bl2_plat_get_bl31_params(void)
{
bl2_to_bl31_params_mem_t *bl31_params_mem;
/*
* Allocate the memory for all the arguments that needs to
* be passed to BL31
*/
bl31_params_mem = (bl2_to_bl31_params_mem_t *)PARAMS_BASE;
memset((void *)PARAMS_BASE, 0, sizeof(bl2_to_bl31_params_mem_t));
/* Assign memory for TF related information */
bl2_to_bl31_params = &bl31_params_mem->bl31_params;
SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
/* Fill BL31 related information */
bl31_ep_info = &bl31_params_mem->bl31_ep_info;
bl2_to_bl31_params->bl31_image_info = &bl31_params_mem->bl31_image_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
VERSION_1, 0);
/* Fill BL32 related information if it exists */
if (BL32_BASE) {
bl2_to_bl31_params->bl32_ep_info =
&bl31_params_mem->bl32_ep_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info,
PARAM_EP, VERSION_1, 0);
bl2_to_bl31_params->bl32_image_info =
&bl31_params_mem->bl32_image_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info,
PARAM_IMAGE_BINARY,
VERSION_1, 0);
}
/* Fill BL33 related information */
bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem->bl33_ep_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
PARAM_EP, VERSION_1, 0);
bl2_to_bl31_params->bl33_image_info = &bl31_params_mem->bl33_image_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
VERSION_1, 0);
return bl2_to_bl31_params;
}
/*******************************************************************************
* This function returns a pointer to the shared memory that the platform
* has kept to point to entry point information of BL31 to BL2
******************************************************************************/
struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
{
#if DEBUG
bl31_ep_info->args.arg1 = FVP_BL31_PLAT_PARAM_VAL;
#endif
return bl31_ep_info;
}
/*******************************************************************************
* BL1 has passed the extents of the trusted SRAM that should be visible to BL2
* in x0. This memory layout is sitting at the base of the free trusted SRAM.
* Copy it to a safe loaction before its reclaimed by later BL2 functionality.
******************************************************************************/
void bl2_early_platform_setup(meminfo_t *mem_layout)
{
/* Initialize the console to provide early debug support */
console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
arm_bl2_early_platform_setup(mem_layout);
/* Initialize the platform config for future decision making */
fvp_config_setup();
/* Initialise the IO layer and register platform IO devices */
fvp_io_setup();
}
/*******************************************************************************
* Perform platform specific setup. For now just initialize the memory location
* to use for passing arguments to BL31.
******************************************************************************/
void bl2_platform_setup(void)
{
/*
* Do initial security configuration to allow DRAM/device access. On
* Base FVP only DRAM security is programmable (via TrustZone), but
* other platforms might have more programmable security devices
* present.
*/
fvp_security_setup();
}
/* Flush the TF params and the TF plat params */
void bl2_plat_flush_bl31_params(void)
{
flush_dcache_range((unsigned long)PARAMS_BASE, \
sizeof(bl2_to_bl31_params_mem_t));
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
******************************************************************************/
void bl2_plat_arch_setup(void)
{
fvp_configure_mmu_el1(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL2_RO_BASE,
BL2_RO_LIMIT
#if USE_COHERENT_MEM
, BL2_COHERENT_RAM_BASE,
BL2_COHERENT_RAM_LIMIT
#endif
);
}
/*******************************************************************************
* Before calling this function BL31 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL31 and set SPSR and security state.
* On FVP we are only setting the security state, entrypoint
******************************************************************************/
void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
entry_point_info_t *bl31_ep_info)
{
SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
}
/*******************************************************************************
* Before calling this function BL32 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL32 and set SPSR and security state.
* On FVP we are only setting the security state, entrypoint
******************************************************************************/
void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
entry_point_info_t *bl32_ep_info)
{
SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
bl32_ep_info->spsr = fvp_get_spsr_for_bl32_entry();
}
/*******************************************************************************
* Before calling this function BL33 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL33 and set SPSR and security state.
* On FVP we are only setting the security state, entrypoint
******************************************************************************/
void bl2_plat_set_bl33_ep_info(image_info_t *image,
entry_point_info_t *bl33_ep_info)
{
SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
bl33_ep_info->spsr = fvp_get_spsr_for_bl33_entry();
}
/*******************************************************************************
* Populate the extents of memory available for loading BL32
******************************************************************************/
void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
{
/*
* Populate the extents of memory available for loading BL32.
*/
bl32_meminfo->total_base = BL32_BASE;
bl32_meminfo->free_base = BL32_BASE;
bl32_meminfo->total_size =
(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
bl32_meminfo->free_size =
(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
}
/*******************************************************************************
* Populate the extents of memory available for loading BL33
******************************************************************************/
void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
{
bl33_meminfo->total_base = DRAM1_NS_BASE;
bl33_meminfo->total_size = DRAM1_NS_SIZE;
bl33_meminfo->free_base = DRAM1_NS_BASE;
bl33_meminfo->free_size = DRAM1_NS_SIZE;
}

219
plat/fvp/bl31_fvp_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -28,225 +28,30 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <arch_helpers.h>
#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <bl31.h>
#include <console.h>
#include <mmio.h>
#include <platform.h>
#include <stddef.h>
#include "drivers/pwrc/fvp_pwrc.h"
#include "fvp_def.h"
#include <plat_arm.h>
#include "fvp_private.h"
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
extern unsigned long __RO_START__;
extern unsigned long __RO_END__;
extern unsigned long __BL31_END__;
#if USE_COHERENT_MEM
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
#endif
/*
* The next 3 constants identify the extents of the code, RO data region and the
* limit of the BL3-1 image. These addresses are used by the MMU setup code and
* therefore they must be page-aligned. It is the responsibility of the linker
* script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL31_END (unsigned long)(&__BL31_END__)
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
#if RESET_TO_BL31
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
#else
/*******************************************************************************
* Reference to structure which holds the arguments that have been passed to
* BL31 from BL2.
******************************************************************************/
static bl31_params_t *bl2_to_bl31_params;
#endif
/*******************************************************************************
* Return a pointer to the 'entry_point_info' structure of the next image for the
* security state specified. BL33 corresponds to the non-secure image type
* while BL32 corresponds to the secure image type. A NULL pointer is returned
* if the image does not exist.
******************************************************************************/
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
#if RESET_TO_BL31
assert(sec_state_is_valid(type));
if (type == NON_SECURE)
return &bl33_image_ep_info;
else
return &bl32_image_ep_info;
#else
entry_point_info_t *next_image_info;
assert(sec_state_is_valid(type));
next_image_info = (type == NON_SECURE) ?
bl2_to_bl31_params->bl33_ep_info :
bl2_to_bl31_params->bl32_ep_info;
/* None of the images on this platform can have 0x0 as the entrypoint */
if (next_image_info->pc)
return next_image_info;
else
return NULL;
#endif
}
/*******************************************************************************
* Perform any BL31 specific platform actions. Here is an opportunity to copy
* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
* are lost (potentially). This needs to be done before the MMU is initialized
* so that the memory layout can be used while creating page tables. On the FVP
* we know that BL2 has populated the parameters in secure DRAM. So we just use
* the reference passed in 'from_bl2' instead of copying. The 'data' parameter
* is not used since all the information is contained in 'from_bl2'. Also, BL2
* has flushed this information to memory, so we are guaranteed to pick up good
* data
******************************************************************************/
void bl31_early_platform_setup(bl31_params_t *from_bl2,
void *plat_params_from_bl2)
{
/* Initialize the console to provide early debug support */
console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2);
/* Initialize the platform config for future decision making */
fvp_config_setup();
#if RESET_TO_BL31
/* There are no parameters from BL2 if BL31 is a reset vector */
assert(from_bl2 == NULL);
assert(plat_params_from_bl2 == NULL);
/*
* Do initial security configuration to allow DRAM/device access. On
* Base FVP only DRAM security is programmable (via TrustZone), but
* other platforms might have more programmable security devices
* present.
* Initialize CCI for this cluster during cold boot.
* No need for locks as no other CPU is active.
*/
fvp_security_setup();
/* Populate entry point information for BL3-2 and BL3-3 */
SET_PARAM_HEAD(&bl32_image_ep_info,
PARAM_EP,
VERSION_1,
0);
SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
bl32_image_ep_info.pc = BL32_BASE;
bl32_image_ep_info.spsr = fvp_get_spsr_for_bl32_entry();
SET_PARAM_HEAD(&bl33_image_ep_info,
PARAM_EP,
VERSION_1,
0);
/*
* Tell BL31 where the non-trusted software image
* is located and the entry state information
*/
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
bl33_image_ep_info.spsr = fvp_get_spsr_for_bl33_entry();
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
#else
/* Check params passed from BL2 should not be NULL,
* We are not checking plat_params_from_bl2 as NULL as we are not
* using it on FVP
*/
assert(from_bl2 != NULL);
assert(from_bl2->h.type == PARAM_BL31);
assert(from_bl2->h.version >= VERSION_1);
bl2_to_bl31_params = from_bl2;
assert(((unsigned long)plat_params_from_bl2) == FVP_BL31_PLAT_PARAM_VAL);
#endif
}
/*******************************************************************************
* Initialize the gic, configure the CLCD and zero out variables needed by the
* secondaries to boot up correctly.
******************************************************************************/
void bl31_platform_setup(void)
{
unsigned int reg_val;
/* Initialize the gic cpu and distributor interfaces */
fvp_gic_init();
arm_gic_setup();
/*
* TODO: Configure the CLCD before handing control to
* linux. Need to see if a separate driver is needed
* instead.
*/
mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0);
mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
(1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16));
/* Enable and initialize the System level generic timer */
mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
/* Allow access to the System counter timer module */
reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val);
mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1));
mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
/* Intialize the power controller */
fvp_pwrc_setup();
/* Topologies are best known to the platform. */
fvp_setup_topology();
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
fvp_cci_init();
#if RESET_TO_BL31
/*
* Enable CCI coherency for the primary CPU's cluster
* (if earlier BL has not already done so).
* FVP PSCI code will enable coherency for other clusters.
*/
fvp_cci_enable();
#endif
fvp_configure_mmu_el3(BL31_RO_BASE,
(BL31_END - BL31_RO_BASE),
BL31_RO_BASE,
BL31_RO_LIMIT
#if USE_COHERENT_MEM
, BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT
#endif
);
#endif /* RESET_TO_BL31 */
}

40
plat/fvp/drivers/pwrc/fvp_pwrc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
#include <bakery_lock.h>
#include <mmio.h>
#include <plat_arm.h>
#include "../../fvp_def.h"
#include "../../fvp_private.h"
#include "fvp_pwrc.h"
@ -38,12 +39,7 @@
* TODO: Someday there will be a generic power controller api. At the moment
* each platform has its own pwrc so just exporting functions is fine.
*/
#if USE_COHERENT_MEM
static bakery_lock_t pwrc_lock __attribute__ ((section("tzfw_coherent_mem")));
#define LOCK_ARG &pwrc_lock
#else
#define LOCK_ARG FVP_PWRC_BAKERY_ID
#endif
ARM_INSTANTIATE_LOCK
unsigned int fvp_pwrc_get_cpu_wkr(unsigned long mpidr)
{
@ -53,56 +49,54 @@ unsigned int fvp_pwrc_get_cpu_wkr(unsigned long mpidr)
unsigned int fvp_pwrc_read_psysr(unsigned long mpidr)
{
unsigned int rc;
fvp_lock_get(LOCK_ARG);
arm_lock_get();
mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
rc = mmio_read_32(PWRC_BASE + PSYSR_OFF);
fvp_lock_release(LOCK_ARG);
arm_lock_release();
return rc;
}
void fvp_pwrc_write_pponr(unsigned long mpidr)
{
fvp_lock_get(LOCK_ARG);
arm_lock_get();
mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr);
fvp_lock_release(LOCK_ARG);
arm_lock_release();
}
void fvp_pwrc_write_ppoffr(unsigned long mpidr)
{
fvp_lock_get(LOCK_ARG);
arm_lock_get();
mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr);
fvp_lock_release(LOCK_ARG);
arm_lock_release();
}
void fvp_pwrc_set_wen(unsigned long mpidr)
{
fvp_lock_get(LOCK_ARG);
arm_lock_get();
mmio_write_32(PWRC_BASE + PWKUPR_OFF,
(unsigned int) (PWKUPR_WEN | mpidr));
fvp_lock_release(LOCK_ARG);
arm_lock_release();
}
void fvp_pwrc_clr_wen(unsigned long mpidr)
{
fvp_lock_get(LOCK_ARG);
arm_lock_get();
mmio_write_32(PWRC_BASE + PWKUPR_OFF,
(unsigned int) mpidr);
fvp_lock_release(LOCK_ARG);
arm_lock_release();
}
void fvp_pwrc_write_pcoffr(unsigned long mpidr)
{
fvp_lock_get(LOCK_ARG);
arm_lock_get();
mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr);
fvp_lock_release(LOCK_ARG);
arm_lock_release();
}
/* Nothing else to do here apart from initializing the lock */
int fvp_pwrc_setup(void)
void plat_arm_pwrc_setup(void)
{
fvp_lock_init(LOCK_ARG);
return 0;
arm_lock_init();
}

3
plat/fvp/drivers/pwrc/fvp_pwrc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -63,7 +63,6 @@
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
int fvp_pwrc_setup(void);
void fvp_pwrc_write_pcoffr(unsigned long);
void fvp_pwrc_write_ppoffr(unsigned long);
void fvp_pwrc_write_pponr(unsigned long);

255
plat/fvp/fvp_def.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -31,214 +31,59 @@
#ifndef __FVP_DEF_H__
#define __FVP_DEF_H__
/* Firmware Image Package */
#define FIP_IMAGE_NAME "fip.bin"
#include <arm_def.h>
#define FVP_MAX_CPUS_PER_CLUSTER 4
#define FVP_PRIMARY_CPU 0x0
/* Memory location options for TSP */
#define FVP_TRUSTED_SRAM_ID 0
#define FVP_TRUSTED_DRAM_ID 1
#define FVP_DRAM_ID 2
/*
* Some of the definitions in this file use the 'ull' suffix in order to avoid
* subtle integer overflow errors due to implicit integer type promotion when
* working with 32-bit values.
*
* The TSP linker script includes some of these definitions to define the BL3-2
* memory map, but the GNU LD does not support the 'ull' suffix, causing the
* build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x)
* will add the 'ull' suffix only when the macro __LINKER__ is not defined
* (__LINKER__ is defined in the command line to preprocess the linker script).
* Constants in the linker script will not have the 'ull' suffix, but this is
* not a problem since the linker evaluates all constant expressions to 64 bit
* (assuming the target architecture is 64 bit).
*/
#ifndef __LINKER__
#define MAKE_ULL(x) x##ull
#else
#define MAKE_ULL(x) x
#endif
/*******************************************************************************
* FVP memory map related constants
******************************************************************************/
#define FVP_TRUSTED_ROM_BASE 0x00000000
#define FVP_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
#define FLASH1_BASE 0x0c000000
#define FLASH1_SIZE 0x04000000
/* The first 4KB of Trusted SRAM are used as shared memory */
#define FVP_SHARED_MEM_BASE 0x04000000
#define FVP_SHARED_MEM_SIZE 0x00001000 /* 4 KB */
#define PSRAM_BASE 0x14000000
#define PSRAM_SIZE 0x04000000
/* The remaining Trusted SRAM is used to load the BL images */
#define FVP_TRUSTED_SRAM_BASE 0x04001000
#define FVP_TRUSTED_SRAM_SIZE 0x0003F000 /* 252 KB */
#define FVP_TRUSTED_DRAM_BASE 0x06000000
#define FVP_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
#define FLASH0_BASE 0x08000000
#define FLASH0_SIZE 0x04000000
#define FLASH1_BASE 0x0c000000
#define FLASH1_SIZE 0x04000000
#define PSRAM_BASE 0x14000000
#define PSRAM_SIZE 0x04000000
#define VRAM_BASE 0x18000000
#define VRAM_SIZE 0x02000000
#define VRAM_BASE 0x18000000
#define VRAM_SIZE 0x02000000
/* Aggregate of all devices in the first GB */
#define DEVICE0_BASE 0x1a000000
#define DEVICE0_SIZE 0x12200000
#define DEVICE0_BASE 0x20000000
#define DEVICE0_SIZE 0x0c200000
#define DEVICE1_BASE 0x2f000000
#define DEVICE1_SIZE 0x200000
#define DEVICE1_BASE 0x2f000000
#define DEVICE1_SIZE 0x200000
#define NSRAM_BASE 0x2e000000
#define NSRAM_SIZE 0x10000
#define NSRAM_BASE 0x2e000000
#define NSRAM_SIZE 0x10000
#define DRAM1_BASE MAKE_ULL(0x80000000)
#define DRAM1_SIZE MAKE_ULL(0x80000000)
#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1)
#define PCIE_EXP_BASE 0x40000000
#define TZRNG_BASE 0x7fe60000
#define TZNVCTR_BASE 0x7fe70000
#define TZROOTKEY_BASE 0x7fe80000
/* Define the top 16 MB of DRAM1 as secure */
#define DRAM1_SEC_SIZE MAKE_ULL(0x01000000)
#define DRAM1_SEC_BASE (DRAM1_BASE + DRAM1_SIZE - DRAM1_SEC_SIZE)
#define DRAM1_SEC_END (DRAM1_SEC_BASE + DRAM1_SEC_SIZE - 1)
/* Constants to distinguish FVP type */
#define HBI_BASE_FVP 0x020
#define REV_BASE_FVP_V0 0x0
#define DRAM1_NS_BASE DRAM1_BASE
#define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_SEC_SIZE)
#define DRAM1_NS_END (DRAM1_NS_BASE + DRAM1_NS_SIZE - 1)
#define HBI_FOUNDATION_FVP 0x010
#define REV_FOUNDATION_FVP_V2_0 0x0
#define REV_FOUNDATION_FVP_V2_1 0x1
#define REV_FOUNDATION_FVP_v9_1 0x2
#define DRAM_BASE DRAM1_BASE
#define DRAM_SIZE DRAM1_SIZE
#define BLD_GIC_VE_MMAP 0x0
#define BLD_GIC_A53A57_MMAP 0x1
#define DRAM2_BASE MAKE_ULL(0x880000000)
#define DRAM2_SIZE MAKE_ULL(0x780000000)
#define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1)
#define PCIE_EXP_BASE 0x40000000
#define TZRNG_BASE 0x7fe60000
#define TZNVCTR_BASE 0x7fe70000
#define TZROOTKEY_BASE 0x7fe80000
/* Memory mapped Generic timer interfaces */
#define SYS_CNTCTL_BASE 0x2a430000
#define SYS_CNTREAD_BASE 0x2a800000
#define SYS_TIMCTL_BASE 0x2a810000
/* V2M motherboard system registers & offsets */
#define VE_SYSREGS_BASE 0x1c010000
#define V2M_SYS_ID 0x0
#define V2M_SYS_SWITCH 0x4
#define V2M_SYS_LED 0x8
#define V2M_SYS_CFGDATA 0xa0
#define V2M_SYS_CFGCTRL 0xa4
#define V2M_SYS_CFGSTATUS 0xa8
#define CFGCTRL_START (1 << 31)
#define CFGCTRL_RW (1 << 30)
#define CFGCTRL_FUNC_SHIFT 20
#define CFGCTRL_FUNC(fn) (fn << CFGCTRL_FUNC_SHIFT)
#define FUNC_CLK_GEN 0x01
#define FUNC_TEMP 0x04
#define FUNC_DB_RESET 0x05
#define FUNC_SCC_CFG 0x06
#define FUNC_SHUTDOWN 0x08
#define FUNC_REBOOT 0x09
/*
* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#if USE_COHERENT_MEM
#define FVP_BL_REGIONS 3
#else
#define FVP_BL_REGIONS 2
#endif
/*
* The FVP_MAX_MMAP_REGIONS depend on the number of entries in fvp_mmap[]
* defined for each BL stage in fvp_common.c.
*/
#if IMAGE_BL1
#define FVP_MMAP_ENTRIES 5
#endif
#if IMAGE_BL2
#define FVP_MMAP_ENTRIES 7
#endif
#if IMAGE_BL31
#define FVP_MMAP_ENTRIES 4
#endif
#if IMAGE_BL32
#define FVP_MMAP_ENTRIES 3
#endif
/* Load address of BL33 in the FVP port */
#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
/* Special value used to verify platform parameters from BL2 to BL3-1 */
#define FVP_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
/*
* V2M sysled bit definitions. The values written to this
* register are defined in arch.h & runtime_svc.h. Only
* used by the primary cpu to diagnose any cold boot issues.
*
* SYS_LED[0] - Security state (S=0/NS=1)
* SYS_LED[2:1] - Exception Level (EL3-EL0)
* SYS_LED[7:3] - Exception Class (Sync/Async & origin)
*
*/
#define SYS_LED_SS_SHIFT 0x0
#define SYS_LED_EL_SHIFT 0x1
#define SYS_LED_EC_SHIFT 0x3
#define SYS_LED_SS_MASK 0x1
#define SYS_LED_EL_MASK 0x3
#define SYS_LED_EC_MASK 0x1f
/* V2M sysid register bits */
#define SYS_ID_REV_SHIFT 28
#define SYS_ID_HBI_SHIFT 16
#define SYS_ID_BLD_SHIFT 12
#define SYS_ID_ARCH_SHIFT 8
#define SYS_ID_FPGA_SHIFT 0
#define SYS_ID_REV_MASK 0xf
#define SYS_ID_HBI_MASK 0xfff
#define SYS_ID_BLD_MASK 0xf
#define SYS_ID_ARCH_MASK 0xf
#define SYS_ID_FPGA_MASK 0xff
#define SYS_ID_BLD_LENGTH 4
#define HBI_FVP_BASE 0x020
#define REV_FVP_BASE_V0 0x0
#define HBI_FOUNDATION 0x010
#define REV_FOUNDATION_V2_0 0x0
#define REV_FOUNDATION_V2_1 0x1
#define BLD_GIC_VE_MMAP 0x0
#define BLD_GIC_A53A57_MMAP 0x1
#define ARCH_MODEL 0x1
#define ARCH_MODEL 0x1
/* FVP Power controller base address*/
#define PWRC_BASE 0x1c100000
#define PWRC_BASE 0x1c100000
/*******************************************************************************
* CCI-400 related constants
******************************************************************************/
#define CCI400_BASE 0x2c090000
#define CCI400_CLUSTER0_SL_IFACE_IX 3
#define CCI400_CLUSTER1_SL_IFACE_IX 4
/*******************************************************************************
* GIC-400 & interrupt handling related constants
******************************************************************************/
@ -256,39 +101,11 @@
#define BASE_GICV_BASE 0x2c02f000
#define IRQ_TZ_WDOG 56
#define IRQ_SEC_PHY_TIMER 29
#define IRQ_SEC_SGI_0 8
#define IRQ_SEC_SGI_1 9
#define IRQ_SEC_SGI_2 10
#define IRQ_SEC_SGI_3 11
#define IRQ_SEC_SGI_4 12
#define IRQ_SEC_SGI_5 13
#define IRQ_SEC_SGI_6 14
#define IRQ_SEC_SGI_7 15
/*******************************************************************************
* PL011 related constants
******************************************************************************/
#define PL011_UART0_BASE 0x1c090000
#define PL011_UART1_BASE 0x1c0a0000
#define PL011_UART2_BASE 0x1c0b0000
#define PL011_UART3_BASE 0x1c0c0000
#define PL011_BAUDRATE 115200
#define PL011_UART0_CLK_IN_HZ 24000000
#define PL011_UART1_CLK_IN_HZ 24000000
#define PL011_UART2_CLK_IN_HZ 24000000
#define PL011_UART3_CLK_IN_HZ 24000000
/*******************************************************************************
* TrustZone address space controller related constants
******************************************************************************/
#define TZC400_BASE 0x2a4a0000
/*
* The NSAIDs for this platform as used to program the TZC400.
*/
/* NSAIDs used by devices in TZC filter 0 on FVP */
#define FVP_NSAID_DEFAULT 0
@ -306,10 +123,8 @@
******************************************************************************/
/* Entrypoint mailboxes */
#define MBOX_BASE FVP_SHARED_MEM_BASE
#define MBOX_SIZE 0x200
#define MBOX_BASE ARM_SHARED_RAM_BASE
#define MBOX_SIZE 0x200
/* Base address where parameters to BL31 are stored */
#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE)
#endif /* __FVP_DEF_H__ */

281
plat/fvp/fvp_io_storage.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -31,227 +31,13 @@
#include <assert.h>
#include <debug.h>
#include <io_driver.h>
#include <io_fip.h>
#include <io_memmap.h>
#include <io_storage.h>
#include <io_semihosting.h>
#include <platform_def.h>
#include <semihosting.h> /* For FOPEN_MODE_... */
#include <string.h>
#include <plat_arm.h>
/* IO devices */
static const io_dev_connector_t *sh_dev_con;
static uintptr_t sh_dev_spec;
static uintptr_t sh_init_params;
static uintptr_t sh_dev_handle;
static const io_dev_connector_t *fip_dev_con;
static uintptr_t fip_dev_spec;
static uintptr_t fip_dev_handle;
static const io_dev_connector_t *memmap_dev_con;
static uintptr_t memmap_dev_spec;
static uintptr_t memmap_init_params;
static uintptr_t memmap_dev_handle;
static const io_block_spec_t fip_block_spec = {
.offset = FLASH0_BASE,
.length = FLASH0_SIZE
};
static const io_file_spec_t bl2_file_spec = {
.path = BL2_IMAGE_NAME,
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t bl31_file_spec = {
.path = BL31_IMAGE_NAME,
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t bl32_file_spec = {
.path = BL32_IMAGE_NAME,
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t bl33_file_spec = {
.path = BL33_IMAGE_NAME,
.mode = FOPEN_MODE_RB
};
#if TRUSTED_BOARD_BOOT
static const io_file_spec_t bl2_cert_file_spec = {
.path = BL2_CERT_NAME,
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t trusted_key_cert_file_spec = {
.path = TRUSTED_KEY_CERT_NAME,
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t bl30_key_cert_file_spec = {
.path = BL30_KEY_CERT_NAME,
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t bl31_key_cert_file_spec = {
.path = BL31_KEY_CERT_NAME,
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t bl32_key_cert_file_spec = {
.path = BL32_KEY_CERT_NAME,
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t bl33_key_cert_file_spec = {
.path = BL33_KEY_CERT_NAME,
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t bl30_cert_file_spec = {
.path = BL30_CERT_NAME,
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t bl31_cert_file_spec = {
.path = BL31_CERT_NAME,
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t bl32_cert_file_spec = {
.path = BL32_CERT_NAME,
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t bl33_cert_file_spec = {
.path = BL33_CERT_NAME,
.mode = FOPEN_MODE_RB
};
#endif /* TRUSTED_BOARD_BOOT */
static int open_fip(const uintptr_t spec);
static int open_memmap(const uintptr_t spec);
struct plat_io_policy {
char *image_name;
uintptr_t *dev_handle;
uintptr_t image_spec;
int (*check)(const uintptr_t spec);
};
static const struct plat_io_policy policies[] = {
{
FIP_IMAGE_NAME,
&memmap_dev_handle,
(uintptr_t)&fip_block_spec,
open_memmap
}, {
BL2_IMAGE_NAME,
&fip_dev_handle,
(uintptr_t)&bl2_file_spec,
open_fip
}, {
BL31_IMAGE_NAME,
&fip_dev_handle,
(uintptr_t)&bl31_file_spec,
open_fip
}, {
BL32_IMAGE_NAME,
&fip_dev_handle,
(uintptr_t)&bl32_file_spec,
open_fip
}, {
BL33_IMAGE_NAME,
&fip_dev_handle,
(uintptr_t)&bl33_file_spec,
open_fip
}, {
#if TRUSTED_BOARD_BOOT
BL2_CERT_NAME,
&fip_dev_handle,
(uintptr_t)&bl2_cert_file_spec,
open_fip
}, {
TRUSTED_KEY_CERT_NAME,
&fip_dev_handle,
(uintptr_t)&trusted_key_cert_file_spec,
open_fip
}, {
BL30_KEY_CERT_NAME,
&fip_dev_handle,
(uintptr_t)&bl30_key_cert_file_spec,
open_fip
}, {
BL31_KEY_CERT_NAME,
&fip_dev_handle,
(uintptr_t)&bl31_key_cert_file_spec,
open_fip
}, {
BL32_KEY_CERT_NAME,
&fip_dev_handle,
(uintptr_t)&bl32_key_cert_file_spec,
open_fip
}, {
BL33_KEY_CERT_NAME,
&fip_dev_handle,
(uintptr_t)&bl33_key_cert_file_spec,
open_fip
}, {
BL30_CERT_NAME,
&fip_dev_handle,
(uintptr_t)&bl30_cert_file_spec,
open_fip
}, {
BL31_CERT_NAME,
&fip_dev_handle,
(uintptr_t)&bl31_cert_file_spec,
open_fip
}, {
BL32_CERT_NAME,
&fip_dev_handle,
(uintptr_t)&bl32_cert_file_spec,
open_fip
}, {
BL33_CERT_NAME,
&fip_dev_handle,
(uintptr_t)&bl33_cert_file_spec,
open_fip
}, {
#endif /* TRUSTED_BOARD_BOOT */
0, 0, 0
}
};
static int open_fip(const uintptr_t spec)
{
int result = IO_FAIL;
/* See if a Firmware Image Package is available */
result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_NAME);
if (result == IO_SUCCESS) {
VERBOSE("Using FIP\n");
/*TODO: Check image defined in spec is present in FIP. */
}
return result;
}
static int open_memmap(const uintptr_t spec)
{
int result = IO_FAIL;
uintptr_t local_image_handle;
result = io_dev_init(memmap_dev_handle, memmap_init_params);
if (result == IO_SUCCESS) {
result = io_open(memmap_dev_handle, spec, &local_image_handle);
if (result == IO_SUCCESS) {
VERBOSE("Using Memmap IO\n");
io_close(local_image_handle);
}
}
return result;
}
static int open_semihosting(const uintptr_t spec)
@ -260,7 +46,7 @@ static int open_semihosting(const uintptr_t spec)
uintptr_t local_image_handle;
/* See if the file exists on semi-hosting.*/
result = io_dev_init(sh_dev_handle, sh_init_params);
result = io_dev_init(sh_dev_handle, (uintptr_t)NULL);
if (result == IO_SUCCESS) {
result = io_open(sh_dev_handle, spec, &local_image_handle);
if (result == IO_SUCCESS) {
@ -271,68 +57,31 @@ static int open_semihosting(const uintptr_t spec)
return result;
}
void fvp_io_setup (void)
void plat_arm_io_setup(void)
{
int io_result = IO_FAIL;
int io_result;
/* Register the IO devices on this platform */
arm_io_setup();
/* Register the additional IO devices on this platform */
io_result = register_io_dev_sh(&sh_dev_con);
assert(io_result == IO_SUCCESS);
io_result = register_io_dev_fip(&fip_dev_con);
assert(io_result == IO_SUCCESS);
io_result = register_io_dev_memmap(&memmap_dev_con);
assert(io_result == IO_SUCCESS);
/* Open connections to devices and cache the handles */
io_result = io_dev_open(sh_dev_con, sh_dev_spec, &sh_dev_handle);
assert(io_result == IO_SUCCESS);
io_result = io_dev_open(fip_dev_con, fip_dev_spec, &fip_dev_handle);
assert(io_result == IO_SUCCESS);
io_result = io_dev_open(memmap_dev_con, memmap_dev_spec,
&memmap_dev_handle);
io_result = io_dev_open(sh_dev_con, (uintptr_t)NULL, &sh_dev_handle);
assert(io_result == IO_SUCCESS);
/* Ignore improbable errors in release builds */
(void)io_result;
}
/* Return an IO device handle and specification which can be used to access
* an image. Use this to enforce platform load policy */
int plat_get_image_source(const char *image_name, uintptr_t *dev_handle,
uintptr_t *image_spec)
int plat_arm_get_alt_image_source(
const uintptr_t image_spec,
uintptr_t *dev_handle)
{
int result = IO_FAIL;
const struct plat_io_policy *policy;
int result = open_semihosting(image_spec);
if (result == IO_SUCCESS)
*dev_handle = sh_dev_handle;
if ((image_name != NULL) && (dev_handle != NULL) &&
(image_spec != NULL)) {
policy = policies;
while (policy->image_name != NULL) {
if (strcmp(policy->image_name, image_name) == 0) {
result = policy->check(policy->image_spec);
if (result == IO_SUCCESS) {
*image_spec = policy->image_spec;
*dev_handle = *(policy->dev_handle);
break;
} else {
result = open_semihosting(
policy->image_spec);
if (result == IO_SUCCESS) {
*dev_handle = sh_dev_handle;
*image_spec =
policy->image_spec;
}
}
}
policy++;
}
} else {
result = IO_FAIL;
}
return result;
}

87
plat/fvp/fvp_pm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -29,21 +29,25 @@
*/
#include <arch_helpers.h>
#include <arm_config.h>
#include <arm_gic.h>
#include <assert.h>
#include <bakery_lock.h>
#include <cci.h>
#include <debug.h>
#include <errno.h>
#include <mmio.h>
#include <platform.h>
#include <plat_config.h>
#include <platform_def.h>
#include <plat_arm.h>
#include <psci.h>
#include <errno.h>
#include <v2m_def.h>
#include "drivers/pwrc/fvp_pwrc.h"
#include "fvp_def.h"
#include "fvp_private.h"
typedef volatile struct mailbox {
unsigned long value __aligned(CACHE_WRITEBACK_GRANULE);
} mailbox_t;
/*******************************************************************************
* Private FVP function to program the mailbox for a cpu before it is released
* from reset.
@ -88,33 +92,6 @@ static void fvp_cluster_pwrdwn_common(void)
fvp_pwrc_write_pcoffr(mpidr);
}
/*******************************************************************************
* Private FVP function which is used to determine if any platform actions
* should be performed for the specified affinity instance given its
* state. Nothing needs to be done if the 'state' is not off or if this is not
* the highest affinity level which will enter the 'state'.
******************************************************************************/
static int32_t fvp_do_plat_actions(unsigned int afflvl, unsigned int state)
{
unsigned int max_phys_off_afflvl;
assert(afflvl <= MPIDR_AFFLVL1);
if (state != PSCI_STATE_OFF)
return -EAGAIN;
/*
* Find the highest affinity level which will be suspended and postpone
* all the platform specific actions until that level is hit.
*/
max_phys_off_afflvl = psci_get_max_phys_off_afflvl();
assert(max_phys_off_afflvl != PSCI_INVALID_DATA);
if (afflvl != max_phys_off_afflvl)
return -EAGAIN;
return 0;
}
/*******************************************************************************
* FVP handler called when an affinity instance is about to enter standby.
******************************************************************************/
@ -179,7 +156,7 @@ void fvp_affinst_off(unsigned int afflvl,
unsigned int state)
{
/* Determine if any platform actions need to be executed */
if (fvp_do_plat_actions(afflvl, state) == -EAGAIN)
if (arm_do_affinst_actions(afflvl, state) == -EAGAIN)
return;
/*
@ -212,7 +189,7 @@ void fvp_affinst_suspend(unsigned long sec_entrypoint,
unsigned long mpidr;
/* Determine if any platform actions need to be executed. */
if (fvp_do_plat_actions(afflvl, state) == -EAGAIN)
if (arm_do_affinst_actions(afflvl, state) == -EAGAIN)
return;
/* Get the mpidr for this cpu */
@ -245,7 +222,7 @@ void fvp_affinst_on_finish(unsigned int afflvl,
unsigned long mpidr;
/* Determine if any platform actions need to be executed. */
if (fvp_do_plat_actions(afflvl, state) == -EAGAIN)
if (arm_do_affinst_actions(afflvl, state) == -EAGAIN)
return;
/* Get the mpidr for this cpu */
@ -303,8 +280,10 @@ void fvp_affinst_suspend_finish(unsigned int afflvl,
static void __dead2 fvp_system_off(void)
{
/* Write the System Configuration Control Register */
mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
CFGCTRL_START | CFGCTRL_RW | CFGCTRL_FUNC(FUNC_SHUTDOWN));
mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
V2M_CFGCTRL_START |
V2M_CFGCTRL_RW |
V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN));
wfi();
ERROR("FVP System Off: operation not handled.\n");
panic();
@ -313,37 +292,15 @@ static void __dead2 fvp_system_off(void)
static void __dead2 fvp_system_reset(void)
{
/* Write the System Configuration Control Register */
mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
CFGCTRL_START | CFGCTRL_RW | CFGCTRL_FUNC(FUNC_REBOOT));
mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
V2M_CFGCTRL_START |
V2M_CFGCTRL_RW |
V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT));
wfi();
ERROR("FVP System Reset: operation not handled.\n");
panic();
}
/*******************************************************************************
* FVP handler called to check the validity of the power state parameter.
******************************************************************************/
int fvp_validate_power_state(unsigned int power_state)
{
/* Sanity check the requested state */
if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
/*
* It's possible to enter standby only on affinity level 0
* i.e. a cpu on the fvp. Ignore any other affinity level.
*/
if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
return PSCI_E_INVALID_PARAMS;
}
/*
* We expect the 'state id' to be zero.
*/
if (psci_get_pstate_id(power_state))
return PSCI_E_INVALID_PARAMS;
return PSCI_E_SUCCESS;
}
/*******************************************************************************
* Export the platform handlers to enable psci to invoke them
******************************************************************************/
@ -356,7 +313,7 @@ static const plat_pm_ops_t fvp_plat_pm_ops = {
.affinst_suspend_finish = fvp_affinst_suspend_finish,
.system_off = fvp_system_off,
.system_reset = fvp_system_reset,
.validate_power_state = fvp_validate_power_state
.validate_power_state = arm_validate_power_state
};
/*******************************************************************************

120
plat/fvp/fvp_private.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -31,131 +31,17 @@
#ifndef __FVP_PRIVATE_H__
#define __FVP_PRIVATE_H__
#include <bakery_lock.h>
#include <bl_common.h>
#include <cpu_data.h>
#include <platform_def.h>
typedef volatile struct mailbox {
unsigned long value
__attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
} mailbox_t;
/*******************************************************************************
* This structure represents the superset of information that is passed to
* BL31 e.g. while passing control to it from BL2 which is bl31_params
* and bl31_plat_params and its elements
******************************************************************************/
typedef struct bl2_to_bl31_params_mem {
bl31_params_t bl31_params;
image_info_t bl31_image_info;
image_info_t bl32_image_info;
image_info_t bl33_image_info;
entry_point_info_t bl33_ep_info;
entry_point_info_t bl32_ep_info;
entry_point_info_t bl31_ep_info;
} bl2_to_bl31_params_mem_t;
#if USE_COHERENT_MEM
/*
* These are wrapper macros to the Coherent Memory Bakery Lock API.
*/
#define fvp_lock_init(_lock_arg) bakery_lock_init(_lock_arg)
#define fvp_lock_get(_lock_arg) bakery_lock_get(_lock_arg)
#define fvp_lock_release(_lock_arg) bakery_lock_release(_lock_arg)
#else
/*******************************************************************************
* Constants to specify how many bakery locks this platform implements. These
* are used if the platform chooses not to use coherent memory for bakery lock
* data structures.
******************************************************************************/
#define FVP_MAX_BAKERIES 1
#define FVP_PWRC_BAKERY_ID 0
/*******************************************************************************
* Definition of structure which holds platform specific per-cpu data. Currently
* it holds only the bakery lock information for each cpu. Constants to
* specify how many bakeries this platform implements and bakery ids are
* specified in fvp_def.h
******************************************************************************/
typedef struct fvp_cpu_data {
bakery_info_t pcpu_bakery_info[FVP_MAX_BAKERIES];
} fvp_cpu_data_t;
/* Macro to define the offset of bakery_info_t in fvp_cpu_data_t */
#define FVP_CPU_DATA_LOCK_OFFSET __builtin_offsetof\
(fvp_cpu_data_t, pcpu_bakery_info)
/*******************************************************************************
* Helper macros for bakery lock api when using the above fvp_cpu_data_t for
* bakery lock data structures. It assumes that the bakery_info is at the
* beginning of the platform specific per-cpu data.
******************************************************************************/
#define fvp_lock_init(_lock_arg) /* No init required */
#define fvp_lock_get(_lock_arg) bakery_lock_get(_lock_arg, \
CPU_DATA_PLAT_PCPU_OFFSET + \
FVP_CPU_DATA_LOCK_OFFSET)
#define fvp_lock_release(_lock_arg) bakery_lock_release(_lock_arg, \
CPU_DATA_PLAT_PCPU_OFFSET + \
FVP_CPU_DATA_LOCK_OFFSET)
/*
* Ensure that the size of the FVP specific per-cpu data structure and the size
* of the memory allocated in generic per-cpu data for the platform are the same.
*/
CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(fvp_cpu_data_t), \
fvp_pcpu_data_size_mismatch);
#endif /* __USE_COHERENT_MEM__ */
#include <plat_arm.h>
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
void fvp_configure_mmu_el1(unsigned long total_base,
unsigned long total_size,
unsigned long,
unsigned long
#if USE_COHERENT_MEM
, unsigned long,
unsigned long
#endif
);
void fvp_configure_mmu_el3(unsigned long total_base,
unsigned long total_size,
unsigned long,
unsigned long
#if USE_COHERENT_MEM
, unsigned long,
unsigned long
#endif
);
int fvp_config_setup(void);
void fvp_config_setup(void);
void fvp_cci_init(void);
void fvp_cci_enable(void);
void fvp_cci_disable(void);
void fvp_gic_init(void);
/* Declarations for fvp_topology.c */
int fvp_setup_topology(void);
/* Declarations for fvp_io_storage.c */
void fvp_io_setup(void);
/* Declarations for fvp_security.c */
void fvp_security_setup(void);
/* Gets the SPR for BL32 entry */
uint32_t fvp_get_spsr_for_bl32_entry(void);
/* Gets the SPSR for BL33 entry */
uint32_t fvp_get_spsr_for_bl33_entry(void);
#endif /* __FVP_PRIVATE_H__ */

98
plat/fvp/fvp_security.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -28,23 +28,13 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <assert.h>
#include <debug.h>
#include <plat_config.h>
#include <tzc400.h>
#include "fvp_def.h"
#include "fvp_private.h"
/* Used to improve readability for configuring regions. */
#define FILTER_SHIFT(filter) (1 << filter)
#include <arm_config.h>
#include <plat_arm.h>
/*
* For the moment we assume that all security programming is done by the
* primary core.
* TODO:
* Might want to enable interrupt on violations when supported?
* We assume that all security programming is done by the primary core.
*/
void fvp_security_setup(void)
void plat_arm_security_setup(void)
{
/*
* The Base FVP has a TrustZone address space controller, the Foundation
@ -55,80 +45,6 @@ void fvp_security_setup(void)
* configurations, those would be configured here.
*/
if (!(get_plat_config()->flags & CONFIG_HAS_TZC))
return;
/*
* The TrustZone controller controls access to main DRAM. Give
* full NS access for the moment to use with OS.
*/
INFO("Configuring TrustZone Controller\n");
/*
* The driver does some error checking and will assert.
* - Provide base address of device on platform.
* - Provide width of ACE-Lite IDs on platform.
*/
tzc_init(TZC400_BASE);
/*
* Currently only filters 0 and 2 are connected on Base FVP.
* Filter 0 : CPU clusters (no access to DRAM by default)
* Filter 1 : not connected
* Filter 2 : LCDs (access to VRAM allowed by default)
* Filter 3 : not connected
* Programming unconnected filters will have no effect at the
* moment. These filter could, however, be connected in future.
* So care should be taken not to configure the unused filters.
*/
/* Disable all filters before programming. */
tzc_disable_filters();
/*
* Allow only non-secure access to all DRAM to supported devices.
* Give access to the CPUs and Virtio. Some devices
* would normally use the default ID so allow that too. We use
* two regions to cover the blocks of physical memory in the FVPs
* plus one region to reserve some memory as secure.
*
* Software executing in the secure state, such as a secure
* boot-loader, can access the DRAM by using the NS attributes in
* the MMU translation tables and descriptors.
*/
/* Region 1 set to cover the Non-Secure DRAM */
tzc_configure_region(FILTER_SHIFT(0), 1,
DRAM1_NS_BASE, DRAM1_NS_END,
TZC_REGION_S_NONE,
TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD));
/* Region 2 set to cover the Secure DRAM */
tzc_configure_region(FILTER_SHIFT(0), 2,
DRAM1_SEC_BASE, DRAM1_SEC_END,
TZC_REGION_S_RDWR,
0x0);
/* Region 3 set to cover the second block of DRAM */
tzc_configure_region(FILTER_SHIFT(0), 3,
DRAM2_BASE, DRAM2_END, TZC_REGION_S_NONE,
TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD));
/*
* TODO: Interrupts are not currently supported. The only
* options we have are for access errors to occur quietly or to
* cause an exception. We choose to cause an exception.
*/
tzc_set_action(TZC_ACTION_ERR);
/* Enable filters. */
tzc_enable_filters();
if (get_arm_config()->flags & ARM_CONFIG_HAS_TZC)
arm_tzc_setup();
}

14
plat/fvp/fvp_topology.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -28,11 +28,13 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <assert.h>
#include <platform_def.h>
/* TODO: Reusing psci error codes & state information. Get our own! */
#include <psci.h>
#include "drivers/pwrc/fvp_pwrc.h"
#include "fvp_def.h"
/* We treat '255' as an invalid affinity instance */
#define AFFINST_INVAL 0xff
@ -57,7 +59,7 @@ typedef struct affinity_info {
* is a separate array for each affinity level i.e. cpus and clusters. The child
* and sibling references allow traversal inside and in between the two arrays.
******************************************************************************/
static affinity_info_t fvp_aff1_topology_map[PLATFORM_CLUSTER_COUNT];
static affinity_info_t fvp_aff1_topology_map[ARM_CLUSTER_COUNT];
static affinity_info_t fvp_aff0_topology_map[PLATFORM_CORE_COUNT];
/* Simple global variable to safeguard us from stupidity */
@ -113,7 +115,7 @@ unsigned int plat_get_aff_count(unsigned int aff_lvl,
case 0:
/* Assert if the cluster id is anything apart from 0 or 1 */
parent_aff_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
assert(parent_aff_id < PLATFORM_CLUSTER_COUNT);
assert(parent_aff_id < ARM_CLUSTER_COUNT);
/* Fetch the starting index in the aff0 array */
for (ctr = fvp_aff1_topology_map[parent_aff_id].child;
@ -181,19 +183,19 @@ unsigned int plat_get_aff_state(unsigned int aff_lvl,
* the FVP flavour its running on. We construct all the mpidrs we can handle
* and rely on the PWRC.PSYSR to flag absent cpus when their status is queried.
******************************************************************************/
int fvp_setup_topology(void)
int plat_arm_topology_setup(void)
{
unsigned char aff0, aff1, aff_state, aff0_offset = 0;
unsigned long mpidr;
topology_setup_done = 0;
for (aff1 = 0; aff1 < PLATFORM_CLUSTER_COUNT; aff1++) {
for (aff1 = 0; aff1 < ARM_CLUSTER_COUNT; aff1++) {
fvp_aff1_topology_map[aff1].child = aff0_offset;
fvp_aff1_topology_map[aff1].sibling = aff1 + 1;
for (aff0 = 0; aff0 < PLATFORM_MAX_CPUS_PER_CLUSTER; aff0++) {
for (aff0 = 0; aff0 < FVP_MAX_CPUS_PER_CLUSTER; aff0++) {
mpidr = aff1 << MPIDR_AFF1_SHIFT;
mpidr |= aff0 << MPIDR_AFF0_SHIFT;

45
plat/fvp/fvp_trusted_boot.c
View File

@ -1,45 +0,0 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <assert.h>
#include <debug.h>
#include "fvp_def.h"
#include "fvp_private.h"
/*
* Check the validity of the key
*
* 0 = success, Otherwise = error
*/
int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
{
/* TODO: check against the ROT key stored in the platform */
return 0;
}

81
plat/fvp/include/plat_macros.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,33 +30,26 @@
#ifndef __PLAT_MACROS_S__
#define __PLAT_MACROS_S__
#include <cci.h>
#include <gic_v2.h>
#include <plat_config.h>
#include <arm_macros.S>
#include <v2m_def.h>
#include "../fvp_def.h"
.section .rodata.gic_reg_name, "aS"
gicc_regs:
.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
gicd_pend_reg:
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
newline:
.asciz "\n"
spacer:
.asciz ":\t\t0x"
/* ---------------------------------------------
* The below macro prints out relevant GIC
* registers whenever an unhandled exception is
* taken in BL3-1.
* The below required platform porting macro
* prints out relevant GIC registers whenever an
* unhandled exception is taken in BL3-1.
* Clobbers: x0 - x10, x16, x17, sp
* ---------------------------------------------
*/
.macro plat_print_gic_regs
mov_imm x0, (VE_SYSREGS_BASE + V2M_SYS_ID)
/*
* Detect if we're using the base memory map or
* the legacy VE memory map
*/
mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID)
ldr w16, [x0]
/* Extract BLD (12th - 15th bits) from the SYS_ID */
ubfx x16, x16, #SYS_ID_BLD_SHIFT, #4
ubfx x16, x16, #V2M_SYS_ID_BLD_SHIFT, #4
/* Check if VE mmap */
cmp w16, #BLD_GIC_VE_MMAP
b.eq use_ve_mmap
@ -70,55 +63,7 @@ use_ve_mmap:
mov_imm x17, VE_GICC_BASE
mov_imm x16, VE_GICD_BASE
print_gicc_regs:
/* gicc base address is now in x17 */
adr x6, gicc_regs /* Load the gicc reg list to x6 */
/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
ldr w8, [x17, #GICC_HPPIR]
ldr w9, [x17, #GICC_AHPPIR]
ldr w10, [x17, #GICC_CTLR]
/* Store to the crash buf and print to console */
bl str_in_crash_buf_print
/* Print the GICD_ISPENDR regs */
add x7, x16, #GICD_ISPENDR
adr x4, gicd_pend_reg
bl asm_print_str
gicd_ispendr_loop:
sub x4, x7, x16
cmp x4, #0x280
b.eq exit_print_gic_regs
bl asm_print_hex
adr x4, spacer
bl asm_print_str
ldr x4, [x7], #8
bl asm_print_hex
adr x4, newline
bl asm_print_str
b gicd_ispendr_loop
exit_print_gic_regs:
.endm
.section .rodata.cci_reg_name, "aS"
cci_iface_regs:
.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
/* ------------------------------------------------
* The below macro prints out relevant interconnect
* registers whenever an unhandled exception is
* taken in BL3-1.
* Clobbers: x0 - x9, sp
* ------------------------------------------------
*/
.macro plat_print_interconnect_regs
adr x6, cci_iface_regs
/* Store in x7 the base address of the first interface */
mov_imm x7, (CCI400_BASE + SLAVE_IFACE3_OFFSET)
ldr w8, [x7, #SNOOP_CTRL_REG]
/* Store in x7 the base address of the second interface */
mov_imm x7, (CCI400_BASE + SLAVE_IFACE4_OFFSET)
ldr w9, [x7, #SNOOP_CTRL_REG]
/* Store to the crash buf and print to console */
bl str_in_crash_buf_print
arm_print_gic_regs
.endm
#endif /* __PLAT_MACROS_S__ */

252
plat/fvp/include/platform_def.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -31,203 +31,83 @@
#ifndef __PLATFORM_DEF_H__
#define __PLATFORM_DEF_H__
#include <arch.h>
#include <arm_def.h>
#include <board_arm_def.h>
#include <common_def.h>
#include <tzc400.h>
#include <v2m_def.h>
#include "../fvp_def.h"
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
/*******************************************************************************
* Generic platform constants
******************************************************************************/
/* Size of cacheable stacks */
#if DEBUG_XLAT_TABLE
#define PLATFORM_STACK_SIZE 0x800
#elif IMAGE_BL1
#if TRUSTED_BOARD_BOOT
#define PLATFORM_STACK_SIZE 0x1000
#else
#define PLATFORM_STACK_SIZE 0x440
#endif
#elif IMAGE_BL2
#if TRUSTED_BOARD_BOOT
#define PLATFORM_STACK_SIZE 0x1000
#else
#define PLATFORM_STACK_SIZE 0x400
#endif
#elif IMAGE_BL31
#define PLATFORM_STACK_SIZE 0x400
#elif IMAGE_BL32
#define PLATFORM_STACK_SIZE 0x440
#endif
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
/* Trusted Boot Firmware BL2 */
#define BL2_IMAGE_NAME "bl2.bin"
/* EL3 Runtime Firmware BL31 */
#define BL31_IMAGE_NAME "bl31.bin"
/* Secure Payload BL32 (Trusted OS) */
#define BL32_IMAGE_NAME "bl32.bin"
/* Non-Trusted Firmware BL33 */
#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
#if TRUSTED_BOARD_BOOT
/* Certificates */
# define BL2_CERT_NAME "bl2.crt"
# define TRUSTED_KEY_CERT_NAME "trusted_key.crt"
# define BL30_KEY_CERT_NAME "bl30_key.crt"
# define BL31_KEY_CERT_NAME "bl31_key.crt"
# define BL32_KEY_CERT_NAME "bl32_key.crt"
# define BL33_KEY_CERT_NAME "bl33_key.crt"
# define BL30_CERT_NAME "bl30.crt"
# define BL31_CERT_NAME "bl31.crt"
# define BL32_CERT_NAME "bl32.crt"
# define BL33_CERT_NAME "bl33.crt"
#endif /* TRUSTED_BOARD_BOOT */
#define PLATFORM_CLUSTER_COUNT 2ull
#define PLATFORM_CLUSTER0_CORE_COUNT 4
#define PLATFORM_CLUSTER1_CORE_COUNT 4
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
PLATFORM_CLUSTER0_CORE_COUNT)
#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
#define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT)
#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
/*******************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
* addresses.
******************************************************************************/
#define BL1_RO_BASE FVP_TRUSTED_ROM_BASE
#define BL1_RO_LIMIT (FVP_TRUSTED_ROM_BASE \
+ FVP_TRUSTED_ROM_SIZE)
/*
* Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
* the current BL1 RW debug size plus a little space for growth.
* Most platform porting definitions provided by included headers
*/
#if TRUSTED_BOARD_BOOT
#define BL1_RW_BASE (FVP_TRUSTED_SRAM_BASE \
+ FVP_TRUSTED_SRAM_SIZE - 0x8000)
#else
#define BL1_RW_BASE (FVP_TRUSTED_SRAM_BASE \
+ FVP_TRUSTED_SRAM_SIZE - 0x6000)
#endif
#define BL1_RW_LIMIT (FVP_TRUSTED_SRAM_BASE \
+ FVP_TRUSTED_SRAM_SIZE)
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
/*
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth.
*/
#if TRUSTED_BOARD_BOOT
#define BL2_BASE (BL31_BASE - 0x1C000)
#else
#define BL2_BASE (BL31_BASE - 0xC000)
#endif
#define BL2_LIMIT BL31_BASE
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
/*
* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
* current BL3-1 debug size plus a little space for growth.
*/
#define BL31_BASE (FVP_TRUSTED_SRAM_BASE \
+ FVP_TRUSTED_SRAM_SIZE - 0x1D000)
#define BL31_PROGBITS_LIMIT BL1_RW_BASE
#define BL31_LIMIT (FVP_TRUSTED_SRAM_BASE \
+ FVP_TRUSTED_SRAM_SIZE)
/*******************************************************************************
* BL32 specific defines.
******************************************************************************/
/*
* On FVP, the TSP can execute from Trusted SRAM, Trusted DRAM or the DRAM
* region secured by the TrustZone controller.
*/
#if FVP_TSP_RAM_LOCATION_ID == FVP_TRUSTED_SRAM_ID
# define TSP_SEC_MEM_BASE FVP_TRUSTED_SRAM_BASE
# define TSP_SEC_MEM_SIZE FVP_TRUSTED_SRAM_SIZE
# define TSP_PROGBITS_LIMIT BL2_BASE
# define BL32_BASE FVP_TRUSTED_SRAM_BASE
# define BL32_LIMIT BL31_BASE
#elif FVP_TSP_RAM_LOCATION_ID == FVP_TRUSTED_DRAM_ID
# define TSP_SEC_MEM_BASE FVP_TRUSTED_DRAM_BASE
# define TSP_SEC_MEM_SIZE FVP_TRUSTED_DRAM_SIZE
# define BL32_BASE FVP_TRUSTED_DRAM_BASE
# define BL32_LIMIT (FVP_TRUSTED_DRAM_BASE + (1 << 21))
#elif FVP_TSP_RAM_LOCATION_ID == FVP_DRAM_ID
# define TSP_SEC_MEM_BASE DRAM1_SEC_BASE
# define TSP_SEC_MEM_SIZE DRAM1_SEC_SIZE
# define BL32_BASE DRAM1_SEC_BASE
# define BL32_LIMIT (DRAM1_SEC_BASE + DRAM1_SEC_SIZE)
#else
# error "Unsupported FVP_TSP_RAM_LOCATION_ID value"
#endif
/*
* ID of the secure physical generic timer interrupt used by the TSP.
* Required ARM standard platform porting definitions
*/
#define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER
#define PLAT_ARM_CLUSTER0_CORE_COUNT 4
#define PLAT_ARM_CLUSTER1_CORE_COUNT 4
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define ADDR_SPACE_SIZE (1ull << 32)
#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
#define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
#if IMAGE_BL1
# define MAX_XLAT_TABLES 2
#elif IMAGE_BL2
# define MAX_XLAT_TABLES 3
#elif IMAGE_BL31
# define MAX_XLAT_TABLES 2
#elif IMAGE_BL32
# if FVP_TSP_RAM_LOCATION_ID == FVP_DRAM_ID
# define MAX_XLAT_TABLES 3
# else
# define MAX_XLAT_TABLES 2
# endif
#endif
#define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000
#define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
#define MAX_MMAP_REGIONS (FVP_MMAP_ENTRIES + FVP_BL_REGIONS)
/* No SCP in FVP */
#define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x0)
/*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.
******************************************************************************/
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x780000000)
#define PLAT_ARM_SHARED_RAM_CACHED 1
/*
* Load address of BL3-3 for this platform port
*/
#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000)
/*
* PL011 related constants
*/
#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
#define PLAT_ARM_CRASH_UART_BASE V2M_IOFPGA_UART1_BASE
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE
#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ
/* CCI related constants */
#define PLAT_ARM_CCI_BASE 0x2c090000
#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3
#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4
/* TrustZone controller related constants
*
* Currently only filters 0 and 2 are connected on Base FVP.
* Filter 0 : CPU clusters (no access to DRAM by default)
* Filter 1 : not connected
* Filter 2 : LCDs (access to VRAM allowed by default)
* Filter 3 : not connected
* Programming unconnected filters will have no effect at the
* moment. These filter could, however, be connected in future.
* So care should be taken not to configure the unused filters.
*
* Allow only non-secure access to all DRAM to supported devices.
* Give access to the CPUs and Virtio. Some devices
* would normally use the default ID so allow that too.
*/
#define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT(0)
#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \
TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \
TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \
TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \
TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD))
#if !USE_COHERENT_MEM
/*******************************************************************************
* Size of the per-cpu data in bytes that should be reserved in the generic
* per-cpu data structure for the FVP port.
******************************************************************************/
#define PLAT_PCPU_DATA_SIZE 2
#endif
#endif /* __PLATFORM_DEF_H__ */

40
plat/fvp/include/platform_oid.h
View File

@ -27,43 +27,9 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef PLATFORM_OID_H_
#define PLATFORM_OID_H_
#include "../../../../../include/plat/arm/board/common/board_arm_oid.h"
/*
* This is the list of the different extensions containing relevant information
* to establish the chain of trust.
*
* The OIDs shown here are just an example. Real OIDs should be obtained from
* the ITU-T.
* Required platform OIDs
* (Provided by included header)
*/
/* Non-volatile counter extensions */
#define TZ_FW_NVCOUNTER_OID "1.2.3.1"
#define NTZ_FW_NVCOUNTER_OID "1.2.3.2"
/* BL2 extensions */
#define BL2_HASH_OID "1.2.3.3"
/* Trusted Key extensions */
#define TZ_WORLD_PK_OID "1.2.3.4"
#define NTZ_WORLD_PK_OID "1.2.3.5"
/* BL3-1 extensions */
#define BL31_CONTENT_CERT_PK_OID "1.2.3.6"
#define BL31_HASH_OID "1.2.3.7"
/* BL3-0 extensions */
#define BL30_CONTENT_CERT_PK_OID "1.2.3.8"
#define BL30_HASH_OID "1.2.3.9"
/* BL3-2 extensions */
#define BL32_CONTENT_CERT_PK_OID "1.2.3.10"
#define BL32_HASH_OID "1.2.3.11"
/* BL3-3 extensions */
#define BL33_CONTENT_CERT_PK_OID "1.2.3.12"
#define BL33_HASH_OID "1.2.3.13"
#endif /* PLATFORM_OID_H_ */

74
plat/fvp/platform.mk
View File

@ -1,5 +1,5 @@
#
# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
@ -28,69 +28,45 @@
# POSSIBILITY OF SUCH DAMAGE.
#
# On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
# Trusted SRAM is the default.
FVP_TSP_RAM_LOCATION := tsram
ifeq (${FVP_TSP_RAM_LOCATION}, tsram)
FVP_TSP_RAM_LOCATION_ID := FVP_TRUSTED_SRAM_ID
else ifeq (${FVP_TSP_RAM_LOCATION}, tdram)
FVP_TSP_RAM_LOCATION_ID := FVP_TRUSTED_DRAM_ID
else ifeq (${FVP_TSP_RAM_LOCATION}, dram)
FVP_TSP_RAM_LOCATION_ID := FVP_DRAM_ID
else
$(error "Unsupported FVP_TSP_RAM_LOCATION value")
endif
# Process flags
$(eval $(call add_define,FVP_TSP_RAM_LOCATION_ID))
PLAT_INCLUDES := -Iinclude/plat/arm/board/common \
-Iplat/fvp/include
PLAT_INCLUDES := -Iplat/fvp/include/
PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_semihosting.c \
drivers/io/io_storage.c \
lib/aarch64/xlat_tables.c \
lib/semihosting/semihosting.c \
lib/semihosting/aarch64/semihosting_call.S \
plat/common/aarch64/plat_common.c \
plat/fvp/fvp_io_storage.c
BL1_SOURCES += drivers/arm/cci/cci.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
plat/common/aarch64/platform_up_stack.S \
plat/fvp/bl1_fvp_setup.c \
plat/fvp/aarch64/fvp_common.c \
plat/fvp/aarch64/fvp_helpers.S
BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
plat/common/aarch64/platform_up_stack.S \
plat/fvp/bl2_fvp_setup.c \
plat/fvp/fvp_security.c \
plat/fvp/aarch64/fvp_common.c
BL31_SOURCES += drivers/arm/cci/cci.c \
drivers/arm/gic/arm_gic.c \
drivers/arm/gic/gic_v2.c \
drivers/arm/gic/gic_v3.c \
drivers/arm/tzc400/tzc400.c \
BL1_SOURCES += drivers/io/io_semihosting.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
plat/common/plat_gic.c \
plat/common/aarch64/platform_mp_stack.S \
lib/semihosting/semihosting.c \
lib/semihosting/aarch64/semihosting_call.S \
plat/fvp/aarch64/fvp_helpers.S \
plat/fvp/bl1_fvp_setup.c \
plat/fvp/fvp_io_storage.c
BL2_SOURCES += drivers/io/io_semihosting.c \
lib/semihosting/semihosting.c \
lib/semihosting/aarch64/semihosting_call.S \
plat/fvp/bl2_fvp_setup.c \
plat/fvp/fvp_io_storage.c \
plat/fvp/fvp_security.c
BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
plat/fvp/bl31_fvp_setup.c \
plat/fvp/fvp_pm.c \
plat/fvp/fvp_security.c \
plat/fvp/fvp_topology.c \
plat/fvp/aarch64/fvp_helpers.S \
plat/fvp/aarch64/fvp_common.c \
plat/fvp/drivers/pwrc/fvp_pwrc.c
ifneq (${TRUSTED_BOARD_BOOT},0)
BL1_SOURCES += plat/fvp/fvp_trusted_boot.c
BL2_SOURCES += plat/fvp/fvp_trusted_boot.c
BL1_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c
BL2_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c
endif
include plat/arm/common/arm_common.mk

12
plat/fvp/tsp/tsp-fvp.mk
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@ -1,5 +1,5 @@
#
# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
@ -29,10 +29,6 @@
#
# TSP source files specific to FVP platform
BL32_SOURCES += drivers/arm/gic/arm_gic.c \
drivers/arm/gic/gic_v2.c \
plat/common/aarch64/platform_mp_stack.S \
plat/common/plat_gic.c \
plat/fvp/aarch64/fvp_common.c \
plat/fvp/aarch64/fvp_helpers.S \
plat/fvp/tsp/tsp_fvp_setup.c
BL32_SOURCES += plat/fvp/tsp/tsp_fvp_setup.c
include plat/arm/common/tsp/arm_tsp.mk

77
plat/fvp/tsp/tsp_fvp_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -28,84 +28,13 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <bl_common.h>
#include <console.h>
#include <platform_tsp.h>
#include "../fvp_def.h"
#include <plat_arm.h>
#include "../fvp_private.h"
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
extern unsigned long __RO_START__;
extern unsigned long __RO_END__;
extern unsigned long __BL32_END__;
#if USE_COHERENT_MEM
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
#endif
/*
* The next 3 constants identify the extents of the code & RO data region and
* the limit of the BL3-2 image. These addresses are used by the MMU setup code
* and therefore they must be page-aligned. It is the responsibility of the
* linker script to ensure that __RO_START__, __RO_END__ & & __BL32_END__
* linker symbols refer to page-aligned addresses.
*/
#define BL32_RO_BASE (unsigned long)(&__RO_START__)
#define BL32_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL32_END (unsigned long)(&__BL32_END__)
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
/*******************************************************************************
* Initialize the UART
******************************************************************************/
void tsp_early_platform_setup(void)
{
/*
* Initialize a different console than already in use to display
* messages from TSP
*/
console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
arm_tsp_early_platform_setup();
/* Initialize the platform config for future decision making */
fvp_config_setup();
}
/*******************************************************************************
* Perform platform specific setup placeholder
******************************************************************************/
void tsp_platform_setup(void)
{
fvp_gic_init();
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the MMU
******************************************************************************/
void tsp_plat_arch_setup(void)
{
fvp_configure_mmu_el1(BL32_RO_BASE,
(BL32_END - BL32_RO_BASE),
BL32_RO_BASE,
BL32_RO_LIMIT
#if USE_COHERENT_MEM
, BL32_COHERENT_RAM_BASE,
BL32_COHERENT_RAM_LIMIT
#endif
);
}