From 612b4a3f2d2929b6b8fd9dd211c8488050e10183 Mon Sep 17 00:00:00 2001 From: Heyi Guo Date: Tue, 19 May 2020 16:45:17 +0800 Subject: [PATCH] drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64() ESPI register offset should also be shifted right by REG##R_SHIFT to keep consistent. It is not a functional issue, for GICD_OFFSET_64() is only used for GICD_IROUTER, and IROUTER_SHIFT is 0. Signed-off-by: Heyi Guo Change-Id: I76eee5c50e4300890e78e80bddde135ce88daa2d --- drivers/arm/gic/v3/gicv3_private.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h index c5d027da2..416cdd018 100644 --- a/drivers/arm/gic/v3/gicv3_private.h +++ b/drivers/arm/gic/v3/gicv3_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -48,7 +48,8 @@ #define GICD_OFFSET_64(REG, id) \ (((id) <= MAX_SPI_ID) ? \ GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \ - GICD_##REG##RE + (((uintptr_t)(id) - MIN_ESPI_ID) << 3)) + GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \ + REG##R_SHIFT) << 3)) #else /* GICv3 */ #define GICD_OFFSET_8(REG, id) \