plat/arm/board/arm_fpga: Enable position-independent execution

This allows the BL31 port to run with position-independent execution
enabled so that it can be ran from any address in the system.
This increases the flexibility of the image, allowing it to be ran from
other locations rather than only its hardcoded absolute address
(currently set to the typical DRAM base of 2GB). This may be useful for
future images that describe system configurations with other memory
layouts (e.g. where SRAM is included).

It does this by setting ENABLE_PIE=1 and changing the absolute
address to 0. The load address of bl31.bin can then be specified by
the -l [load address] argument in the fpga-run command (additionally,
this address is required by any preceding payloads that specify the
start address. For ELF payloads this is usually extracted automatically
by reading the entrypoint address in the header, however bl31.bin is a
different file format so has this additional dependency).

Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: Idd74787796ab0cf605fe2701163d9c4b3223a143

plat/arm/board/arm_fpga/include/platform_def.h

@@ -8,6 +8,8 @@
 #define PLATFORM_DEF_H
 
 #include <arch.h>
+#include <plat/common/common_def.h>
+#include <platform_def.h>
 #include "../fpga_def.h"
 
 #define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
@@ -25,8 +27,13 @@
 #define PLAT_NUM_PWR_DOMAINS		(FPGA_MAX_CLUSTER_COUNT + \
 					PLATFORM_CORE_COUNT) + 1
 
+#if !ENABLE_PIE
 #define BL31_BASE			UL(0x80000000)
 #define BL31_LIMIT			UL(0x80100000)
+#else
+#define BL31_BASE			UL(0x0)
+#define BL31_LIMIT			UL(0x01000000)
+#endif
 
 #define GICD_BASE			0x30000000
 #define GICR_BASE			0x30040000