Merge "stm32mp1: register shared resource per IOMEM address" into integration
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commit
62cd4a19ef
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@ -8,6 +8,7 @@
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#define STM32MP_SHARED_RESOURCES_H
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#include <stdbool.h>
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#include <stdint.h>
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#ifdef STM32MP_SHARED_RESOURCES
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enum stm32mp_shres;
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@ -24,7 +25,20 @@ void stm32mp_register_secure_periph(enum stm32mp_shres id);
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/* Register a shared resource assigned to the non-secure world */
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void stm32mp_register_non_secure_periph(enum stm32mp_shres id);
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/* Register a peripheral as secure or non-secure based on IO base address */
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void stm32mp_register_secure_periph_iomem(uintptr_t base);
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void stm32mp_register_non_secure_periph_iomem(uintptr_t base);
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/* Consolidate peripheral states and lock against new peripheral registering */
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void stm32mp_lock_periph_registering(void);
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#else
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static inline void stm32mp_register_secure_periph_iomem(uintptr_t base __unused)
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{
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}
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static inline
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void stm32mp_register_non_secure_periph_iomem(uintptr_t base __unused)
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{
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}
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#endif /* STM32MP_SHARED_RESOURCES */
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#endif /* STM32MP_SHARED_RESOURCES_H */
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@ -494,14 +494,16 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
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#define IWDG2_BASE U(0x5A002000)
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/*******************************************************************************
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* STM32MP1 I2C4
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******************************************************************************/
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#define I2C4_BASE U(0x5C002000)
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/*******************************************************************************
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* STM32MP1 DBGMCU
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* Miscellaneous STM32MP1 peripherals base address
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******************************************************************************/
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#define CRYP1_BASE U(0x54001000)
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#define DBGMCU_BASE U(0x50081000)
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#define HASH1_BASE U(0x54002000)
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#define I2C4_BASE U(0x5C002000)
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#define I2C6_BASE U(0x5c009000)
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#define RNG1_BASE U(0x54003000)
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#define RTC_BASE U(0x5c004000)
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#define SPI6_BASE U(0x5c001000)
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/*******************************************************************************
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* Device Tree defines
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@ -233,6 +233,84 @@ void stm32mp_register_non_secure_periph(enum stm32mp_shres id)
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register_periph(id, SHRES_NON_SECURE);
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}
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static void register_periph_iomem(uintptr_t base, unsigned int state)
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{
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enum stm32mp_shres id;
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switch (base) {
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case CRYP1_BASE:
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id = STM32MP1_SHRES_CRYP1;
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break;
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case HASH1_BASE:
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id = STM32MP1_SHRES_HASH1;
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break;
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case I2C4_BASE:
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id = STM32MP1_SHRES_I2C4;
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break;
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case I2C6_BASE:
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id = STM32MP1_SHRES_I2C6;
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break;
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case IWDG1_BASE:
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id = STM32MP1_SHRES_IWDG1;
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break;
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case RNG1_BASE:
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id = STM32MP1_SHRES_RNG1;
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break;
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case RTC_BASE:
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id = STM32MP1_SHRES_RTC;
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break;
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case SPI6_BASE:
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id = STM32MP1_SHRES_SPI6;
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break;
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case USART1_BASE:
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id = STM32MP1_SHRES_USART1;
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break;
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case GPIOA_BASE:
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case GPIOB_BASE:
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case GPIOC_BASE:
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case GPIOD_BASE:
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case GPIOE_BASE:
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case GPIOF_BASE:
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case GPIOG_BASE:
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case GPIOH_BASE:
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case GPIOI_BASE:
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case GPIOJ_BASE:
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case GPIOK_BASE:
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case USART2_BASE:
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case USART3_BASE:
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case UART4_BASE:
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case UART5_BASE:
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case USART6_BASE:
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case UART7_BASE:
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case UART8_BASE:
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case IWDG2_BASE:
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/* Allow drivers to register some non-secure resources */
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VERBOSE("IO for non-secure resource 0x%x\n",
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(unsigned int)base);
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if (state != SHRES_NON_SECURE) {
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panic();
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}
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return;
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default:
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panic();
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}
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register_periph(id, state);
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}
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void stm32mp_register_secure_periph_iomem(uintptr_t base)
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{
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register_periph_iomem(base, SHRES_SECURE);
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}
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void stm32mp_register_non_secure_periph_iomem(uintptr_t base)
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{
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register_periph_iomem(base, SHRES_NON_SECURE);
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}
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static bool stm32mp_gpio_bank_is_non_secure(unsigned int bank)
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{
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unsigned int non_secure = 0U;
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