andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Rework use of interconnect drivers 

ARM Trusted Firmware supports 2 different interconnect peripheral
drivers: CCI and CCN. ARM platforms are implemented using either of the
interconnect peripherals.

This patch adds a layer of abstraction to help ARM platform ports to
choose the right interconnect driver and corresponding platform support.
This is as described below:

1. A set of ARM common functions have been implemented to initialise an
interconnect and for entering/exiting a cluster from coherency. These
functions are prefixed as "plat_arm_interconnect_". Weak definitions of
these functions have been provided for each type of driver.

2.`plat_print_interconnect_regs` macro used for printing CCI registers is
moved from a common arm_macros.S to cci_macros.S.

3. The `ARM_CONFIG_HAS_CCI` flag used in `arm_config_flags` structure
is renamed to `ARM_CONFIG_HAS_INTERCONNECT`.

Change-Id: I02f31184fbf79b784175892d5ce1161b65a0066c
This commit is contained in:
Vikram Kanigiri 2016-02-15 11:54:14 +00:00 committed by Dan Handley
parent 3aef80f5b2
commit 6355f2347a
20 changed files with 286 additions and 112 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
include/plat/arm/common/aarch64/arm_macros.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,7 +30,6 @@
#ifndef __ARM_MACROS_S__
#define __ARM_MACROS_S__
#include <cci.h>
#include <gic_common.h>
#include <gicv2.h>
#include <gicv3.h>
@ -117,31 +116,4 @@ gicd_ispendr_loop:
exit_print_gic_regs:
.endm
.section .rodata.cci_reg_name, "aS"
cci_iface_regs:
.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
/* ------------------------------------------------
* The below required platform porting macro prints
* out relevant interconnect registers whenever an
* unhandled exception is taken in BL31.
* Clobbers: x0 - x9, sp
* ------------------------------------------------
*/
.macro plat_print_interconnect_regs
adr x6, cci_iface_regs
/* Store in x7 the base address of the first interface */
mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX))
ldr w8, [x7, #SNOOP_CTRL_REG]
/* Store in x7 the base address of the second interface */
mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX))
ldr w9, [x7, #SNOOP_CTRL_REG]
/* Store to the crash buf and print to console */
bl str_in_crash_buf_print
.endm
#endif /* __ARM_MACROS_S__ */

61
include/plat/arm/common/aarch64/cci_macros.S Normal file
View File

@ -0,0 +1,61 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CCI_MACROS_S__
#define __CCI_MACROS_S__
#include <cci.h>
#include <platform_def.h>
.section .rodata.cci_reg_name, "aS"
cci_iface_regs:
.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
/* ------------------------------------------------
* The below required platform porting macro prints
* out relevant interconnect registers whenever an
* unhandled exception is taken in BL31.
* Clobbers: x0 - x9, sp
* ------------------------------------------------
*/
.macro plat_print_interconnect_regs
adr x6, cci_iface_regs
/* Store in x7 the base address of the first interface */
mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX))
ldr w8, [x7, #SNOOP_CTRL_REG]
/* Store in x7 the base address of the second interface */
mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX))
ldr w9, [x7, #SNOOP_CTRL_REG]
/* Store to the crash buf and print to console */
bl str_in_crash_buf_print
.endm
#endif /* __CCI_MACROS_S__ */

6
include/plat/arm/common/arm_config.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -35,8 +35,8 @@
enum arm_config_flags {
/* Whether Base memory map is in use */
ARM_CONFIG_BASE_MMAP = 0x1,
/* Whether CCI should be enabled */
ARM_CONFIG_HAS_CCI = 0x2,
/* Whether interconnect should be enabled */
ARM_CONFIG_HAS_INTERCONNECT = 0x2,
/* Whether TZC should be configured */
ARM_CONFIG_HAS_TZC = 0x4
};

6
include/plat/arm/common/plat_arm.h
View File

@ -126,9 +126,6 @@ void arm_configure_mmu_el3(unsigned long total_base,
#endif /* __ARM_RECOM_STATE_ID_ENC__ */
/* CCI utility functions */
void arm_cci_init(void);
/* IO storage utility functions */
void arm_io_setup(void);
@ -189,6 +186,9 @@ void plat_arm_gic_cpuif_disable(void);
void plat_arm_gic_pcpu_init(void);
void plat_arm_security_setup(void);
void plat_arm_pwrc_setup(void);
void plat_arm_interconnect_init(void);
void plat_arm_interconnect_enter_coherency(void);
void plat_arm_interconnect_exit_coherency(void);
/*
* Optional functions required in ARM standard platforms

32
plat/arm/board/fvp/aarch64/fvp_common.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,7 +30,6 @@
#include <arm_config.h>
#include <arm_def.h>
#include <cci.h>
#include <debug.h>
#include <gicv2.h>
#include <mmio.h>
@ -50,9 +49,9 @@ extern gicv2_driver_data_t arm_gic_data;
/*******************************************************************************
* arm_config holds the characteristics of the differences between the three FVP
* platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
* at each boot stage by the primary before enabling the MMU (to allow cci
* configuration) & used thereafter. Each BL will have its own copy to allow
* independent operation.
* at each boot stage by the primary before enabling the MMU (to allow
* interconnect configuration) & used thereafter. Each BL will have its own copy
* to allow independent operation.
******************************************************************************/
arm_config_t arm_config;
@ -209,7 +208,7 @@ void fvp_config_setup(void)
break;
case HBI_BASE_FVP:
arm_config.flags |= ARM_CONFIG_BASE_MMAP |
ARM_CONFIG_HAS_CCI | ARM_CONFIG_HAS_TZC;
ARM_CONFIG_HAS_INTERCONNECT | ARM_CONFIG_HAS_TZC;
/*
* Check for supported revisions
@ -230,23 +229,20 @@ void fvp_config_setup(void)
}
void fvp_cci_init(void)
void fvp_interconnect_init(void)
{
/*
* Initialize CCI-400 driver
*/
if (arm_config.flags & ARM_CONFIG_HAS_CCI)
arm_cci_init();
if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT)
plat_arm_interconnect_init();
}
void fvp_cci_enable(void)
void fvp_interconnect_enable(void)
{
if (arm_config.flags & ARM_CONFIG_HAS_CCI)
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT)
plat_arm_interconnect_enter_coherency();
}
void fvp_cci_disable(void)
void fvp_interconnect_disable(void)
{
if (arm_config.flags & ARM_CONFIG_HAS_CCI)
cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT)
plat_arm_interconnect_exit_coherency();
}

10
plat/arm/board/fvp/fvp_bl1_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -44,14 +44,14 @@ void bl1_early_platform_setup(void)
fvp_config_setup();
/*
* Initialize CCI for this cluster during cold boot.
* Initialize Interconnect for this cluster during cold boot.
* No need for locks as no other CPU is active.
*/
fvp_cci_init();
fvp_interconnect_init();
/*
* Enable CCI coherency for the primary CPU's cluster.
* Enable coherency in Interconnect for the primary CPU's cluster.
*/
fvp_cci_enable();
fvp_interconnect_enable();
}
/*******************************************************************************

12
plat/arm/board/fvp/fvp_bl31_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -41,17 +41,17 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
fvp_config_setup();
/*
* Initialize CCI for this cluster during cold boot.
* No need for locks as no other CPU is active.
* Initialize the correct interconnect for this cluster during cold
* boot. No need for locks as no other CPU is active.
*/
fvp_cci_init();
fvp_interconnect_init();
/*
* Enable CCI coherency for the primary CPU's cluster.
* Enable coherency in interconnect for the primary CPU's cluster.
* Earlier bootloader stages might already do this (e.g. Trusted
* Firmware's BL1 does it) but we can't assume so. There is no harm in
* executing this code twice anyway.
* FVP PSCI code will enable coherency for other clusters.
*/
fvp_cci_enable();
fvp_interconnect_enable();
}

6
plat/arm/board/fvp/fvp_pm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -86,7 +86,7 @@ static void fvp_cluster_pwrdwn_common(void)
uint64_t mpidr = read_mpidr_el1();
/* Disable coherency if this cluster is to be turned off */
fvp_cci_disable();
fvp_interconnect_disable();
/* Program the power controller to turn the cluster off */
fvp_pwrc_write_pcoffr(mpidr);
@ -117,7 +117,7 @@ static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_s
fvp_pwrc_write_pponr(mpidr);
/* Enable coherency if this cluster was off */
fvp_cci_enable();
fvp_interconnect_enable();
}
/*

8
plat/arm/board/fvp/fvp_private.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -39,9 +39,9 @@
void fvp_config_setup(void);
void fvp_cci_init(void);
void fvp_cci_enable(void);
void fvp_cci_disable(void);
void fvp_interconnect_init(void);
void fvp_interconnect_enable(void);
void fvp_interconnect_disable(void);
#endif /* __FVP_PRIVATE_H__ */

3
plat/arm/board/fvp/include/plat_macros.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -31,6 +31,7 @@
#define __PLAT_MACROS_S__
#include <arm_macros.S>
#include <cci_macros.S>
#include <v2m_def.h>
#include "../fvp_def.h"

15
plat/arm/board/fvp/platform.mk
View File

@ -57,10 +57,14 @@ else
$(error "Incorrect GIC driver chosen on FVP port")
endif
FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \
plat/arm/common/arm_cci.c
FVP_SECURITY_SOURCES := drivers/arm/tzc400/tzc400.c \
plat/arm/board/fvp/fvp_security.c \
plat/arm/common/arm_tzc400.c
PLAT_INCLUDES := -Iplat/arm/board/fvp/include
@ -73,13 +77,15 @@ FVP_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a72.S
BL1_SOURCES += drivers/io/io_semihosting.c \
${FVP_CPU_LIBS} \
lib/semihosting/semihosting.c \
lib/semihosting/aarch64/semihosting_call.S \
plat/arm/board/fvp/aarch64/fvp_helpers.S \
plat/arm/board/fvp/fvp_bl1_setup.c \
plat/arm/board/fvp/fvp_err.c \
plat/arm/board/fvp/fvp_io_storage.c
plat/arm/board/fvp/fvp_io_storage.c \
${FVP_CPU_LIBS} \
${FVP_INTERCONNECT_SOURCES}
BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c \
drivers/io/io_semihosting.c \
@ -94,13 +100,14 @@ BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c \
BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \
${FVP_SECURITY_SOURCES}
BL31_SOURCES += ${FVP_CPU_LIBS} \
plat/arm/board/fvp/fvp_bl31_setup.c \
BL31_SOURCES += plat/arm/board/fvp/fvp_bl31_setup.c \
plat/arm/board/fvp/fvp_pm.c \
plat/arm/board/fvp/fvp_topology.c \
plat/arm/board/fvp/aarch64/fvp_helpers.S \
plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c \
${FVP_CPU_LIBS} \
${FVP_GIC_SOURCES} \
${FVP_INTERCONNECT_SOURCES} \
${FVP_SECURITY_SOURCES}
# Disable the PSCI platform compatibility layer

3
plat/arm/board/juno/include/plat_macros.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
#ifndef __PLAT_MACROS_S__
#define __PLAT_MACROS_S__
#include <cci_macros.S>
#include <css_macros.S>
/*

8
plat/arm/board/juno/platform.mk
View File

@ -34,10 +34,14 @@ JUNO_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
plat/common/plat_gicv2.c \
plat/arm/common/arm_gicv2.c
JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \
plat/arm/common/arm_cci.c
JUNO_SECURITY_SOURCES := drivers/arm/tzc400/tzc400.c \
plat/arm/board/juno/juno_security.c \
plat/arm/common/arm_tzc400.c
PLAT_INCLUDES := -Iplat/arm/board/juno/include
PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/aarch64/juno_helpers.S
@ -46,7 +50,8 @@ BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
plat/arm/board/juno/juno_bl1_setup.c \
plat/arm/board/juno/juno_err.c
plat/arm/board/juno/juno_err.c \
${JUNO_INTERCONNECT_SOURCES}
BL2_SOURCES += plat/arm/board/juno/juno_err.c \
${JUNO_SECURITY_SOURCES}
@ -58,6 +63,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a72.S \
plat/arm/board/juno/juno_pm.c \
${JUNO_GIC_SOURCES} \
${JUNO_INTERCONNECT_SOURCES} \
${JUNO_SECURITY_SOURCES}
# Enable workarounds for selected Cortex-A57 erratas.

12
plat/arm/common/aarch64/arm_common.c
View File

@ -29,7 +29,6 @@
*/
#include <arch.h>
#include <arch_helpers.h>
#include <cci.h>
#include <mmio.h>
#include <plat_arm.h>
#include <platform_def.h>
@ -37,11 +36,6 @@
extern const mmap_region_t plat_arm_mmap[];
static const int cci_map[] = {
PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX,
PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX
};
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak plat_get_ns_image_entrypoint
#pragma weak plat_arm_get_mmap
@ -140,12 +134,6 @@ uint32_t arm_get_spsr_for_bl33_entry(void)
return spsr;
}
void arm_cci_init(void)
{
cci_init(PLAT_ARM_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
}
/*******************************************************************************
* Configures access to the system counter timer module.
******************************************************************************/

11
plat/arm/common/arm_bl1_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -31,7 +31,6 @@
#include <arch.h>
#include <arm_def.h>
#include <bl_common.h>
#include <cci.h>
#include <console.h>
#include <platform_def.h>
#include <plat_arm.h>
@ -101,14 +100,14 @@ void bl1_early_platform_setup(void)
arm_bl1_early_platform_setup();
/*
* Initialize CCI for this cluster during cold boot.
* Initialize Interconnect for this cluster during cold boot.
* No need for locks as no other CPU is active.
*/
arm_cci_init();
plat_arm_interconnect_init();
/*
* Enable CCI coherency for the primary CPU's cluster.
* Enable Interconnect coherency for the primary CPU's cluster.
*/
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
plat_arm_interconnect_enter_coherency();
}
/******************************************************************************

11
plat/arm/common/arm_bl31_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -33,7 +33,6 @@
#include <arm_def.h>
#include <assert.h>
#include <bl_common.h>
#include <cci.h>
#include <console.h>
#include <debug.h>
#include <mmio.h>
@ -178,20 +177,20 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2);
/*
* Initialize CCI for this cluster during cold boot.
* Initialize Interconnect for this cluster during cold boot.
* No need for locks as no other CPU is active.
*/
arm_cci_init();
plat_arm_interconnect_init();
/*
* Enable CCI coherency for the primary CPU's cluster.
* Enable Interconnect coherency for the primary CPU's cluster.
* Earlier bootloader stages might already do this (e.g. Trusted
* Firmware's BL1 does it) but we can't assume so. There is no harm in
* executing this code twice anyway.
* Platform specific PSCI code will enable coherency for other
* clusters.
*/
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
plat_arm_interconnect_enter_coherency();
}
/*******************************************************************************

72
plat/arm/common/arm_cci.c Normal file
View File

@ -0,0 +1,72 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <cci.h>
#include <plat_arm.h>
#include <platform_def.h>
static const int cci_map[] = {
PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX,
PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX
};
/******************************************************************************
* The following functions are defined as weak to allow a platform to override
* the way ARM CCI driver is initialised and used.
*****************************************************************************/
#pragma weak plat_arm_interconnect_init
#pragma weak plat_arm_interconnect_enter_coherency
#pragma weak plat_arm_interconnect_exit_coherency
/******************************************************************************
* Helper function to initialize ARM CCI driver.
*****************************************************************************/
void plat_arm_interconnect_init(void)
{
cci_init(PLAT_ARM_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
}
/******************************************************************************
* Helper function to place current master into coherency
*****************************************************************************/
void plat_arm_interconnect_enter_coherency(void)
{
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
}
/******************************************************************************
* Helper function to remove current master from coherency
*****************************************************************************/
void plat_arm_interconnect_exit_coherency(void)
{
cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
}

77
plat/arm/common/arm_ccn.c Normal file
View File

@ -0,0 +1,77 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <ccn.h>
#include <plat_arm.h>
#include <platform_def.h>
static const unsigned char master_to_rn_id_map[] = {
PLAT_ARM_CLUSTER_TO_CCN_ID_MAP
};
static const ccn_desc_t arm_ccn_desc = {
.periphbase = PLAT_ARM_CCN_BASE,
.num_masters = ARRAY_SIZE(master_to_rn_id_map),
.master_to_rn_id_map = master_to_rn_id_map
};
/******************************************************************************
* The following functions are defined as weak to allow a platform to override
* the way ARM CCN driver is initialised and used.
*****************************************************************************/
#pragma weak plat_arm_interconnect_init
#pragma weak plat_arm_interconnect_enter_coherency
#pragma weak plat_arm_interconnect_exit_coherency
/******************************************************************************
* Helper function to initialize ARM CCN driver.
*****************************************************************************/
void plat_arm_interconnect_init(void)
{
ccn_init(&arm_ccn_desc);
}
/******************************************************************************
* Helper function to place current master into coherency
*****************************************************************************/
void plat_arm_interconnect_enter_coherency(void)
{
ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
}
/******************************************************************************
* Helper function to remove current master from coherency
*****************************************************************************/
void plat_arm_interconnect_exit_coherency(void)
{
ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
}

8
plat/arm/common/arm_common.mk
View File

@ -87,9 +87,7 @@ PLAT_BL_COMMON_SOURCES += lib/aarch64/xlat_tables.c \
plat/arm/common/aarch64/arm_helpers.S \
plat/common/aarch64/plat_common.c
BL1_SOURCES += drivers/arm/cci/cci.c \
drivers/arm/ccn/ccn.c \
drivers/arm/sp805/sp805.c \
BL1_SOURCES += drivers/arm/sp805/sp805.c \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
@ -112,9 +110,7 @@ BL2_SOURCES += drivers/io/io_fip.c \
BL2U_SOURCES += plat/arm/common/arm_bl2u_setup.c \
plat/common/aarch64/platform_up_stack.S
BL31_SOURCES += drivers/arm/cci/cci.c \
drivers/arm/ccn/ccn.c \
plat/arm/common/arm_bl31_setup.c \
BL31_SOURCES += plat/arm/common/arm_bl31_setup.c \
plat/arm/common/arm_pm.c \
plat/arm/common/arm_topology.c \
plat/common/aarch64/platform_mp_stack.S \

7
plat/arm/css/common/css_pm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -31,7 +31,6 @@
#include <arch_helpers.h>
#include <assert.h>
#include <cassert.h>
#include <cci.h>
#include <css_pm.h>
#include <debug.h>
#include <errno.h>
@ -108,7 +107,7 @@ static void css_pwr_domain_on_finisher_common(
* if this cluster was off.
*/
if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
plat_arm_interconnect_enter_coherency();
}
/*******************************************************************************
@ -153,7 +152,7 @@ static void css_power_down_common(const psci_power_state_t *target_state)
/* Cluster is to be turned off, so disable coherency */
if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
plat_arm_interconnect_exit_coherency();
cluster_state = scpi_power_off;
}