From 635e6b108e773daf37c00f46e6fbb1cae4e78f96 Mon Sep 17 00:00:00 2001 From: jason-ch chen Date: Tue, 16 Nov 2021 10:18:46 +0800 Subject: [PATCH] feat(mt8186): add Vcore DVFS driver Add Vcore DVFS to SPM driver. TEST=build pass BUG=b:202871018 Signed-off-by: Jason-ch Chen Change-Id: I52b241b2cdb792be74390cbaa09a728ddbe6593a --- plat/mediatek/mt8186/drivers/spm/build.mk | 1 + .../mt8186/drivers/spm/mt_spm_conservation.c | 3 +- .../mt8186/drivers/spm/mt_spm_internal.h | 2 + .../mt8186/drivers/spm/mt_spm_vcorefs.c | 533 ++++++++++++++++++ .../mt8186/drivers/spm/mt_spm_vcorefs.h | 316 +++++++++++ plat/mediatek/mt8186/include/platform_def.h | 1 + plat/mediatek/mt8186/plat_sip_calls.c | 12 +- 7 files changed, 866 insertions(+), 2 deletions(-) create mode 100644 plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.c create mode 100644 plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.h diff --git a/plat/mediatek/mt8186/drivers/spm/build.mk b/plat/mediatek/mt8186/drivers/spm/build.mk index f288691b9..72a2b6b1d 100644 --- a/plat/mediatek/mt8186/drivers/spm/build.mk +++ b/plat/mediatek/mt8186/drivers/spm/build.mk @@ -20,6 +20,7 @@ PLAT_SPM_SOURCE_FILES_COMMON += \ ${CUR_SPM_FOLDER}/mt_spm.c \ ${CUR_SPM_FOLDER}/mt_spm_internal.c \ ${CUR_SPM_FOLDER}/mt_spm_pmic_wrap.c \ + ${CUR_SPM_FOLDER}/mt_spm_vcorefs.c \ ${CUR_SPM_FOLDER}/mt_spm_conservation.c \ ${CUR_SPM_FOLDER}/mt_spm_extern.c diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.c index 0f8dfe8f0..a6ea97735 100644 --- a/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.c +++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -34,7 +35,7 @@ static int go_to_spm_before_wfi(int state_id, unsigned int ext_opand, __spm_set_cpu_status(cpu); __spm_set_power_control(pwrctrl); __spm_set_wakeup_event(pwrctrl); - + __spm_sync_vcore_dvfs_power_control(pwrctrl, __spm_vcorefs.pwrctrl); __spm_set_pcm_flags(pwrctrl); __spm_src_req_update(pwrctrl, resource_req); diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.h index 760900d5f..8cf20625e 100644 --- a/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.h +++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.h @@ -577,6 +577,8 @@ extern void __spm_get_wakeup_status(struct wake_status *wakesta, extern void __spm_clean_after_wakeup(void); extern wake_reason_t __spm_output_wake_reason(int state_id, const struct wake_status *wakesta); +extern void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl, + const struct pwr_ctrl *src_pwr_ctrl); extern void __spm_set_pcm_wdt(int en); extern uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr); extern void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl); diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.c new file mode 100644 index 000000000..fb51e69cc --- /dev/null +++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.c @@ -0,0 +1,533 @@ +/* + * Copyright(C)2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VCORE_CT_ENABLE BIT(5) +#define VCORE_DRM_ENABLE BIT(31) +#define VCORE_PTPOD_SHIFT (8) +#define VCORE_POWER_SHIFT (2) + +#define VCORE_MAX_OPP (3) +#define DRAM_MAX_OPP (6) + +#define SW_REQ5_INIT_VAL (6U << 12) +#define V_VMODE_SHIFT (0) +#define VCORE_HV (105) +#define VCORE_LV (95) +#define PMIC_STEP_UV (6250) + +static int vcore_opp_0_uv = 800000; +static int vcore_opp_1_uv = 700000; +static int vcore_opp_2_uv = 650000; + +static struct pwr_ctrl vcorefs_ctrl = { + .wake_src = R12_REG_CPU_WAKEUP, + + /* default VCORE DVFS is disabled */ + .pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO | + SPM_FLAG_DISABLE_VCORE_DVS | + SPM_FLAG_DISABLE_VCORE_DFS), + + /* Auto-gen Start */ + + /* SPM_AP_STANDBY_CON */ + .reg_wfi_op = 0, + .reg_wfi_type = 0, + .reg_mp0_cputop_idle_mask = 0, + .reg_mp1_cputop_idle_mask = 0, + .reg_mcusys_idle_mask = 0, + .reg_md_apsrc_1_sel = 0, + .reg_md_apsrc_0_sel = 0, + .reg_conn_apsrc_sel = 0, + + /* SPM_SRC6_MASK */ + .reg_ccif_event_infra_req_mask_b = 0xFFFF, + .reg_ccif_event_apsrc_req_mask_b = 0xFFFF, + + /* SPM_SRC_REQ */ + .reg_spm_apsrc_req = 1, + .reg_spm_f26m_req = 1, + .reg_spm_infra_req = 1, + .reg_spm_vrf18_req = 1, + .reg_spm_ddren_req = 1, + .reg_spm_dvfs_req = 0, + .reg_spm_sw_mailbox_req = 0, + .reg_spm_sspm_mailbox_req = 0, + .reg_spm_adsp_mailbox_req = 0, + .reg_spm_scp_mailbox_req = 0, + + /* SPM_SRC_MASK */ + .reg_md_0_srcclkena_mask_b = 1, + .reg_md_0_infra_req_mask_b = 1, + .reg_md_0_apsrc_req_mask_b = 1, + .reg_md_0_vrf18_req_mask_b = 1, + .reg_md_0_ddren_req_mask_b = 1, + .reg_md_1_srcclkena_mask_b = 0, + .reg_md_1_infra_req_mask_b = 0, + .reg_md_1_apsrc_req_mask_b = 0, + .reg_md_1_vrf18_req_mask_b = 0, + .reg_md_1_ddren_req_mask_b = 0, + .reg_conn_srcclkena_mask_b = 1, + .reg_conn_srcclkenb_mask_b = 0, + .reg_conn_infra_req_mask_b = 1, + .reg_conn_apsrc_req_mask_b = 1, + .reg_conn_vrf18_req_mask_b = 1, + .reg_conn_ddren_req_mask_b = 1, + .reg_conn_vfe28_mask_b = 0, + .reg_srcclkeni_srcclkena_mask_b = 1, + .reg_srcclkeni_infra_req_mask_b = 1, + .reg_infrasys_apsrc_req_mask_b = 0, + .reg_infrasys_ddren_req_mask_b = 1, + .reg_sspm_srcclkena_mask_b = 1, + .reg_sspm_infra_req_mask_b = 1, + .reg_sspm_apsrc_req_mask_b = 1, + .reg_sspm_vrf18_req_mask_b = 1, + .reg_sspm_ddren_req_mask_b = 1, + + /* SPM_SRC2_MASK */ + .reg_scp_srcclkena_mask_b = 1, + .reg_scp_infra_req_mask_b = 1, + .reg_scp_apsrc_req_mask_b = 1, + .reg_scp_vrf18_req_mask_b = 1, + .reg_scp_ddren_req_mask_b = 1, + .reg_audio_dsp_srcclkena_mask_b = 1, + .reg_audio_dsp_infra_req_mask_b = 1, + .reg_audio_dsp_apsrc_req_mask_b = 1, + .reg_audio_dsp_vrf18_req_mask_b = 1, + .reg_audio_dsp_ddren_req_mask_b = 1, + .reg_ufs_srcclkena_mask_b = 1, + .reg_ufs_infra_req_mask_b = 1, + .reg_ufs_apsrc_req_mask_b = 1, + .reg_ufs_vrf18_req_mask_b = 1, + .reg_ufs_ddren_req_mask_b = 1, + .reg_disp0_apsrc_req_mask_b = 1, + .reg_disp0_ddren_req_mask_b = 1, + .reg_disp1_apsrc_req_mask_b = 1, + .reg_disp1_ddren_req_mask_b = 1, + .reg_gce_infra_req_mask_b = 1, + .reg_gce_apsrc_req_mask_b = 1, + .reg_gce_vrf18_req_mask_b = 1, + .reg_gce_ddren_req_mask_b = 1, + .reg_apu_srcclkena_mask_b = 0, + .reg_apu_infra_req_mask_b = 0, + .reg_apu_apsrc_req_mask_b = 0, + .reg_apu_vrf18_req_mask_b = 0, + .reg_apu_ddren_req_mask_b = 0, + .reg_cg_check_srcclkena_mask_b = 0, + .reg_cg_check_apsrc_req_mask_b = 0, + .reg_cg_check_vrf18_req_mask_b = 0, + .reg_cg_check_ddren_req_mask_b = 0, + + /* SPM_SRC3_MASK */ + .reg_dvfsrc_event_trigger_mask_b = 1, + .reg_sw2spm_wakeup_mask_b = 0, + .reg_adsp2spm_wakeup_mask_b = 0, + .reg_sspm2spm_wakeup_mask_b = 0, + .reg_scp2spm_wakeup_mask_b = 0, + .reg_csyspwrup_ack_mask = 1, + .reg_spm_reserved_srcclkena_mask_b = 0, + .reg_spm_reserved_infra_req_mask_b = 0, + .reg_spm_reserved_apsrc_req_mask_b = 0, + .reg_spm_reserved_vrf18_req_mask_b = 0, + .reg_spm_reserved_ddren_req_mask_b = 0, + .reg_mcupm_srcclkena_mask_b = 1, + .reg_mcupm_infra_req_mask_b = 1, + .reg_mcupm_apsrc_req_mask_b = 1, + .reg_mcupm_vrf18_req_mask_b = 1, + .reg_mcupm_ddren_req_mask_b = 1, + .reg_msdc0_srcclkena_mask_b = 1, + .reg_msdc0_infra_req_mask_b = 1, + .reg_msdc0_apsrc_req_mask_b = 1, + .reg_msdc0_vrf18_req_mask_b = 1, + .reg_msdc0_ddren_req_mask_b = 1, + .reg_msdc1_srcclkena_mask_b = 1, + .reg_msdc1_infra_req_mask_b = 1, + .reg_msdc1_apsrc_req_mask_b = 1, + .reg_msdc1_vrf18_req_mask_b = 1, + .reg_msdc1_ddren_req_mask_b = 1, + + /* SPM_SRC4_MASK */ + .reg_ccif_event_srcclkena_mask_b = 0x3FF, + .reg_bak_psri_srcclkena_mask_b = 0, + .reg_bak_psri_infra_req_mask_b = 0, + .reg_bak_psri_apsrc_req_mask_b = 0, + .reg_bak_psri_vrf18_req_mask_b = 0, + .reg_bak_psri_ddren_req_mask_b = 0, + .reg_dramc_md32_infra_req_mask_b = 1, + .reg_dramc_md32_vrf18_req_mask_b = 0, + .reg_conn_srcclkenb2pwrap_mask_b = 0, + .reg_dramc_md32_apsrc_req_mask_b = 0, + + /* SPM_SRC5_MASK */ + .reg_mcusys_merge_apsrc_req_mask_b = 0x14, + .reg_mcusys_merge_ddren_req_mask_b = 0x14, + .reg_afe_srcclkena_mask_b = 0, + .reg_afe_infra_req_mask_b = 0, + .reg_afe_apsrc_req_mask_b = 0, + .reg_afe_vrf18_req_mask_b = 0, + .reg_afe_ddren_req_mask_b = 0, + .reg_msdc2_srcclkena_mask_b = 0, + .reg_msdc2_infra_req_mask_b = 0, + .reg_msdc2_apsrc_req_mask_b = 0, + .reg_msdc2_vrf18_req_mask_b = 0, + .reg_msdc2_ddren_req_mask_b = 0, + + /* SPM_WAKEUP_EVENT_MASK */ + .reg_wakeup_event_mask = 0xEFFFFFFF, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + .reg_ext_wakeup_event_mask = 0xFFFFFFFF, + + /* SPM_SRC7_MASK */ + .reg_pcie_srcclkena_mask_b = 1, + .reg_pcie_infra_req_mask_b = 1, + .reg_pcie_apsrc_req_mask_b = 1, + .reg_pcie_vrf18_req_mask_b = 1, + .reg_pcie_ddren_req_mask_b = 1, + .reg_dpmaif_srcclkena_mask_b = 1, + .reg_dpmaif_infra_req_mask_b = 1, + .reg_dpmaif_apsrc_req_mask_b = 1, + .reg_dpmaif_vrf18_req_mask_b = 1, + .reg_dpmaif_ddren_req_mask_b = 1, + + /* Auto-gen End */ +}; + +struct spm_lp_scen __spm_vcorefs = { + .pwrctrl = &vcorefs_ctrl, +}; + +static struct reg_config dvfsrc_init_configs[] = { + {DVFSRC_HRT_REQ_UNIT, 0x0000001E}, + {DVFSRC_DEBOUNCE_TIME, 0x00001965}, + {DVFSRC_TIMEOUT_NEXTREQ, 0x00000015}, + {DVFSRC_VCORE_REQUEST4, 0x22211100}, + {DVFSRC_DDR_QOS0, 0x00000019}, + {DVFSRC_DDR_QOS1, 0x00000026}, + {DVFSRC_DDR_QOS2, 0x00000033}, + {DVFSRC_DDR_QOS3, 0x0000004C}, + {DVFSRC_DDR_QOS4, 0x00000066}, + {DVFSRC_DDR_QOS5, 0x00000077}, + {DVFSRC_DDR_QOS6, 0x00770077}, + {DVFSRC_LEVEL_LABEL_0_1, 0x40225032}, + {DVFSRC_LEVEL_LABEL_2_3, 0x20223012}, + {DVFSRC_LEVEL_LABEL_4_5, 0x40211012}, + {DVFSRC_LEVEL_LABEL_6_7, 0x20213011}, + {DVFSRC_LEVEL_LABEL_8_9, 0x30101011}, + {DVFSRC_LEVEL_LABEL_10_11, 0x10102000}, + {DVFSRC_LEVEL_LABEL_12_13, 0x00000000}, + {DVFSRC_LEVEL_LABEL_14_15, 0x00000000}, + {DVFSRC_LEVEL_LABEL_16_17, 0x00000000}, + {DVFSRC_LEVEL_LABEL_18_19, 0x00000000}, + {DVFSRC_LEVEL_LABEL_20_21, 0x00000000}, + {DVFSRC_LEVEL_MASK, 0x00000000}, + {DVFSRC_MD_LATENCY_IMPROVE, 0x00000020}, + {DVFSRC_HRT_BW_BASE, 0x00000004}, + {DVSFRC_HRT_REQ_MD_URG, 0x000D50D5}, + {DVFSRC_HRT_REQ_MD_BW_0, 0x00200802}, + {DVFSRC_HRT_REQ_MD_BW_1, 0x00200802}, + {DVFSRC_HRT_REQ_MD_BW_2, 0x00200800}, + {DVFSRC_HRT_REQ_MD_BW_3, 0x00400802}, + {DVFSRC_HRT_REQ_MD_BW_4, 0x00601404}, + {DVFSRC_HRT_REQ_MD_BW_5, 0x00D02C09}, + {DVFSRC_HRT_REQ_MD_BW_6, 0x00000012}, + {DVFSRC_HRT_REQ_MD_BW_7, 0x00000024}, + {DVFSRC_HRT_REQ_MD_BW_8, 0x00000000}, + {DVFSRC_HRT_REQ_MD_BW_9, 0x00000000}, + {DVFSRC_HRT_REQ_MD_BW_10, 0x00035400}, + {DVFSRC_HRT1_REQ_MD_BW_0, 0x04B12C4B}, + {DVFSRC_HRT1_REQ_MD_BW_1, 0x04B12C4B}, + {DVFSRC_HRT1_REQ_MD_BW_2, 0x04B12C00}, + {DVFSRC_HRT1_REQ_MD_BW_3, 0x04B12C4B}, + {DVFSRC_HRT1_REQ_MD_BW_4, 0x04B12C4B}, + {DVFSRC_HRT1_REQ_MD_BW_5, 0x04B12C4B}, + {DVFSRC_HRT1_REQ_MD_BW_6, 0x0000004B}, + {DVFSRC_HRT1_REQ_MD_BW_7, 0x0000005C}, + {DVFSRC_HRT1_REQ_MD_BW_8, 0x00000000}, + {DVFSRC_HRT1_REQ_MD_BW_9, 0x00000000}, + {DVFSRC_HRT1_REQ_MD_BW_10, 0x00035400}, + {DVFSRC_95MD_SCEN_BW0_T, 0x22222220}, + {DVFSRC_95MD_SCEN_BW1_T, 0x22222222}, + {DVFSRC_95MD_SCEN_BW2_T, 0x22222222}, + {DVFSRC_95MD_SCEN_BW3_T, 0x52222222}, + {DVFSRC_95MD_SCEN_BW4, 0x00000005}, + {DVFSRC_RSRV_5, 0x00000001}, +#ifdef DVFSRC_1600_FLOOR + {DVFSRC_DDR_REQUEST, 0x00000022}, +#else + {DVFSRC_DDR_REQUEST, 0x00000021}, +#endif + {DVFSRC_DDR_REQUEST3, 0x00554300}, + {DVFSRC_DDR_ADD_REQUEST, 0x55543210}, +#ifdef DVFSRC_1600_FLOOR + {DVFSRC_DDR_REQUEST5, 0x54322000}, +#else + {DVFSRC_DDR_REQUEST5, 0x54321000}, +#endif + {DVFSRC_DDR_REQUEST6, 0x53143130}, + {DVFSRC_DDR_REQUEST7, 0x55000000}, + {DVFSRC_DDR_REQUEST8, 0x05000000}, + {DVFSRC_EMI_MON_DEBOUNCE_TIME, 0x4C2D0000}, + {DVFSRC_EMI_ADD_REQUEST, 0x55543210}, + {DVFSRC_VCORE_USER_REQ, 0x00010A29}, + {DVFSRC_HRT_HIGH, 0x0E100960}, + {DVFSRC_HRT_HIGH_1, 0x1AD21700}, + {DVFSRC_HRT_HIGH_2, 0x314C2306}, + {DVFSRC_HRT_HIGH_3, 0x314C314C}, + {DVFSRC_HRT_LOW, 0x0E0F095F}, + {DVFSRC_HRT_LOW_1, 0x1AD116FF}, + {DVFSRC_HRT_LOW_2, 0x314B2305}, + {DVFSRC_HRT_LOW_3, 0x314B314B}, +#ifdef DVFSRC_1600_FLOOR + {DVFSRC_HRT_REQUEST, 0x55554322}, +#else + {DVFSRC_HRT_REQUEST, 0x55554321}, +#endif + {DVFSRC_BASIC_CONTROL_3, 0x0000000E}, + {DVFSRC_INT_EN, 0x00000002}, + {DVFSRC_QOS_EN, 0x001e407C}, + {DVFSRC_CURRENT_FORCE, 0x00000001}, + {DVFSRC_BASIC_CONTROL, 0x0180004B}, + {DVFSRC_BASIC_CONTROL, 0X0180404B}, + {DVFSRC_BASIC_CONTROL, 0X0180014B}, + {DVFSRC_CURRENT_FORCE, 0x00000000}, +}; + +#define IS_PMIC_57() ((pmic_get_hwcid() >> 8) == 0x57) + +static inline unsigned int vcore_base_uv(void) +{ + static unsigned int vb; + + if (vb == 0) { + vb = IS_PMIC_57() ? 518750 : 500000; + } + + return vb; +} + +#define _VCORE_STEP_UV (6250) + +#define __vcore_uv_to_pmic(uv) /* pmic >= uv */ \ + ((((uv) - vcore_base_uv()) + (_VCORE_STEP_UV - 1)) / _VCORE_STEP_UV) + +static int devinfo_table[] = { + 3539, 492, 1038, 106, 231, 17, 46, 2179, + 4, 481, 1014, 103, 225, 17, 45, 2129, + 3, 516, 1087, 111, 242, 19, 49, 2282, + 4, 504, 1063, 108, 236, 18, 47, 2230, + 4, 448, 946, 96, 210, 15, 41, 1986, + 2, 438, 924, 93, 205, 14, 40, 1941, + 2, 470, 991, 101, 220, 16, 43, 2080, + 3, 459, 968, 98, 215, 16, 42, 2033, + 3, 594, 1250, 129, 279, 23, 57, 2621, + 6, 580, 1221, 126, 273, 22, 56, 2561, + 6, 622, 1309, 136, 293, 24, 60, 2745, + 7, 608, 1279, 132, 286, 23, 59, 2683, + 6, 541, 1139, 117, 254, 20, 51, 2390, + 5, 528, 1113, 114, 248, 19, 50, 2335, + 4, 566, 1193, 123, 266, 21, 54, 2503, + 5, 553, 1166, 120, 260, 21, 53, 2446, + 5, 338, 715, 70, 157, 9, 29, 1505, + 3153, 330, 699, 69, 153, 9, 28, 1470, + 3081, 354, 750, 74, 165, 10, 31, 1576, + 3302, 346, 732, 72, 161, 10, 30, 1540, + 3227, 307, 652, 63, 142, 8, 26, 1371, + 2875, 300, 637, 62, 139, 7, 25, 1340, + 2809, 322, 683, 67, 149, 8, 27, 1436, + 3011, 315, 667, 65, 146, 8, 26, 1404, + 2942, 408, 862, 86, 191, 13, 37, 1811, + 1, 398, 842, 84, 186, 12, 36, 1769, + 1, 428, 903, 91, 200, 14, 39, 1896, + 2, 418, 882, 89, 195, 13, 38, 1853, + 2, 371, 785, 78, 173, 11, 33, 1651, + 3458, 363, 767, 76, 169, 10, 32, 1613, + 3379, 389, 823, 82, 182, 12, 35, 1729, + 1, 380, 804, 80, 177, 11, 34, 1689, +}; + +static void spm_vcorefs_pwarp_cmd(uint64_t cmd, uint64_t val) +{ + if (cmd < NR_IDX_ALL) { + mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val); + } else { + INFO("cmd out of range!\n"); + } +} + +void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue) +{ + mmio_write_32(OPP0_TABLE, 0xFFFF0000); + mmio_write_32(OPP1_TABLE, 0xFFFF0100); + mmio_write_32(OPP2_TABLE, 0xFFFF0300); + mmio_write_32(OPP3_TABLE, 0xFFFF0500); + mmio_write_32(OPP4_TABLE, 0xFFFF0700); + mmio_write_32(OPP5_TABLE, 0xFFFF0202); + mmio_write_32(OPP6_TABLE, 0xFFFF0302); + mmio_write_32(OPP7_TABLE, 0xFFFF0502); + mmio_write_32(OPP8_TABLE, 0xFFFF0702); + mmio_write_32(OPP9_TABLE, 0xFFFF0403); + mmio_write_32(OPP10_TABLE, 0xFFFF0603); + mmio_write_32(OPP11_TABLE, 0xFFFF0803); + mmio_write_32(OPP12_TABLE, 0xFFFF0903); + mmio_write_32(OPP13_TABLE, 0xFFFFFFFF); + mmio_write_32(OPP14_TABLE, 0xFFFFFFFF); + mmio_write_32(OPP15_TABLE, 0xFFFFFFFF); + mmio_write_32(OPP16_TABLE, 0xFFFFFFFF); + mmio_write_32(OPP17_TABLE, 0xFFFFFFFF); + mmio_write_32(SHU0_ARRAY, 0xFFFFFF00); + mmio_write_32(SHU1_ARRAY, 0xFFFFEE01); + mmio_write_32(SHU2_ARRAY, 0xFF05EEFF); + mmio_write_32(SHU3_ARRAY, 0xFF06EE02); + mmio_write_32(SHU4_ARRAY, 0x0906FFFF); + mmio_write_32(SHU5_ARRAY, 0xFF07EE03); + mmio_write_32(SHU6_ARRAY, 0x0A07FFFF); + mmio_write_32(SHU7_ARRAY, 0xFF08EE04); + mmio_write_32(SHU8_ARRAY, 0x0B08FFFF); + mmio_write_32(SHU9_ARRAY, 0x0CFFFFFF); + + mmio_clrsetbits_32(SPM_DVFS_MISC, SPM_DVFS_FORCE_ENABLE_LSB, + SPM_DVFSRC_ENABLE_LSB); + + mmio_write_32(SPM_DVFS_LEVEL, 0x00000001); + mmio_write_32(SPM_DVS_DFS_LEVEL, 0x00010001); +} + +void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl, + const struct pwr_ctrl *src_pwr_ctrl) +{ + uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS | + SPM_FLAG_DISABLE_VCORE_DFS | + SPM_FLAG_ENABLE_VOLTAGE_BIN; + + dest_pwr_ctrl->pcm_flags = (dest_pwr_ctrl->pcm_flags & (~dvfs_mask)) | + (src_pwr_ctrl->pcm_flags & dvfs_mask); + + if (dest_pwr_ctrl->pcm_flags_cust > 0U) { + dest_pwr_ctrl->pcm_flags_cust = + ((dest_pwr_ctrl->pcm_flags_cust) & (~dvfs_mask)) | + ((src_pwr_ctrl->pcm_flags) & (dvfs_mask)); + } +} + +static void spm_go_to_vcorefs(void) +{ + __spm_set_power_control(__spm_vcorefs.pwrctrl); + __spm_set_wakeup_event(__spm_vcorefs.pwrctrl); + __spm_set_pcm_flags(__spm_vcorefs.pwrctrl); + __spm_send_cpu_wakeup_event(); +} + +static void dvfsrc_init(void) +{ + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(dvfsrc_init_configs); i++) { + mmio_write_32(dvfsrc_init_configs[i].offset, + dvfsrc_init_configs[i].val); + } +} + +static void spm_vcorefs_vcore_setting(uint64_t flag) +{ + int idx, ptpod, rsv4; + int power = 0; + + switch (flag) { + case 1: /*HV*/ + vcore_opp_0_uv = 840000; + vcore_opp_1_uv = 725000; + vcore_opp_2_uv = 682500; + break; + case 2: /*LV*/ + vcore_opp_0_uv = 760000; + vcore_opp_1_uv = 665000; + vcore_opp_2_uv = 617500; + break; + default: + break; + } + + rsv4 = mmio_read_32(DVFSRC_RSRV_4); + ptpod = (rsv4 >> VCORE_PTPOD_SHIFT) & 0xF; + idx = (rsv4 >> VCORE_POWER_SHIFT) & 0xFF; + + if (idx != 0) { + power = (int)devinfo_table[idx]; + } + + if (power > 0 && power <= 40) { + idx = ptpod & 0xF; + if (idx == 1) { + vcore_opp_2_uv = 700000; + } else if (idx > 1 && idx < 10) { + vcore_opp_2_uv = 675000; + } + } + + spm_vcorefs_pwarp_cmd(3, __vcore_uv_to_pmic(vcore_opp_2_uv)); + spm_vcorefs_pwarp_cmd(2, __vcore_uv_to_pmic(vcore_opp_1_uv)); + spm_vcorefs_pwarp_cmd(0, __vcore_uv_to_pmic(vcore_opp_0_uv)); +} + +uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4) +{ + uint64_t cmd = x1; + uint64_t spm_flags; + + switch (cmd) { + case VCOREFS_SMC_CMD_INIT: + /* vcore_dvfs init + kick */ + mmio_write_32(DVFSRC_SW_REQ5, SW_REQ5_INIT_VAL); + spm_dvfsfw_init(0ULL, 0ULL); + spm_vcorefs_vcore_setting(x3 & 0xF); + spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO; + if ((x2 & 0x1) > 0U) { + spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS; + } + + if ((x2 & 0x2) > 0U) { + spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS; + } + + if ((mmio_read_32(DVFSRC_RSRV_4) & VCORE_CT_ENABLE) > 0U) { + spm_flags |= SPM_FLAG_ENABLE_VOLTAGE_BIN; + } + + set_pwrctrl_pcm_flags(__spm_vcorefs.pwrctrl, spm_flags); + spm_go_to_vcorefs(); + dvfsrc_init(); + + *x4 = 0U; + mmio_write_32(DVFSRC_SW_REQ5, 0U); + break; + case VCOREFS_SMC_CMD_KICK: + mmio_write_32(DVFSRC_SW_REQ5, 0U); + break; + default: + break; + } + + return 0ULL; +} diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.h new file mode 100644 index 000000000..4fe1b122a --- /dev/null +++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.h @@ -0,0 +1,316 @@ +/* + * Copyright(C)2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SPM_VCOREFS_H +#define MT_SPM_VCOREFS_H + +uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4); + +enum vcorefs_smc_cmd { + VCOREFS_SMC_CMD_0 = 0U, + VCOREFS_SMC_CMD_1 = 1U, + VCOREFS_SMC_CMD_2 = 2U, + VCOREFS_SMC_CMD_3 = 3U, + VCOREFS_SMC_CMD_4 = 4U, + /* check spmfw status */ + VCOREFS_SMC_CMD_5 = 5U, + + /* get spmfw type */ + VCOREFS_SMC_CMD_6 = 6U, + + /* get spm reg status */ + VCOREFS_SMC_CMD_7 = 7U, + + NUM_VCOREFS_SMC_CMD = 8U, +}; + +enum vcorefs_smc_cmd_new { + VCOREFS_SMC_CMD_INIT = 0U, + VCOREFS_SMC_CMD_KICK = 1U, + VCOREFS_SMC_CMD_OPP_TYPE = 2U, + VCOREFS_SMC_CMD_FW_TYPE = 3U, + VCOREFS_SMC_CMD_GET_UV = 4U, + VCOREFS_SMC_CMD_GET_FREQ = 5U, + VCOREFS_SMC_CMD_GET_NUM_V = 6U, + VCOREFS_SMC_CMD_GET_NUM_F = 7U, + VCOREFS_SMC_CMD_FB_ACTION = 8U, + /*chip specific setting */ + VCOREFS_SMC_CMD_SET_FREQ = 16U, + VCOREFS_SMC_CMD_SET_EFUSE = 17U, + VCOREFS_SMC_CMD_GET_EFUSE = 18U, + VCOREFS_SMC_CMD_DVFS_HOPPING = 19U, + VCOREFS_SMC_CMD_DVFS_HOPPING_STATE = 20U, +}; + +enum dvfsrc_channel { + DVFSRC_CHANNEL_1 = 1U, + DVFSRC_CHANNEL_2 = 2U, + DVFSRC_CHANNEL_3 = 3U, + DVFSRC_CHANNEL_4 = 4U, + NUM_DVFSRC_CHANNEL = 5U, +}; + +struct reg_config { + uint32_t offset; + uint32_t val; +}; + +#define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0) +#define DVFSRC_SW_REQ1 (DVFSRC_BASE + 0x4) +#define DVFSRC_SW_REQ2 (DVFSRC_BASE + 0x8) +#define DVFSRC_SW_REQ3 (DVFSRC_BASE + 0xC) +#define DVFSRC_SW_REQ4 (DVFSRC_BASE + 0x10) +#define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14) +#define DVFSRC_SW_REQ6 (DVFSRC_BASE + 0x18) +#define DVFSRC_SW_REQ7 (DVFSRC_BASE + 0x1C) +#define DVFSRC_SW_REQ8 (DVFSRC_BASE + 0x20) +#define DVFSRC_EMI_REQUEST (DVFSRC_BASE + 0x24) +#define DVFSRC_EMI_REQUEST2 (DVFSRC_BASE + 0x28) +#define DVFSRC_EMI_REQUEST3 (DVFSRC_BASE + 0x2C) +#define DVFSRC_EMI_REQUEST4 (DVFSRC_BASE + 0x30) +#define DVFSRC_EMI_REQUEST5 (DVFSRC_BASE + 0x34) +#define DVFSRC_EMI_REQUEST6 (DVFSRC_BASE + 0x38) +#define DVFSRC_EMI_HRT (DVFSRC_BASE + 0x3C) +#define DVFSRC_EMI_HRT2 (DVFSRC_BASE + 0x40) +#define DVFSRC_EMI_HRT3 (DVFSRC_BASE + 0x44) +#define DVFSRC_EMI_QOS0 (DVFSRC_BASE + 0x48) +#define DVFSRC_EMI_QOS1 (DVFSRC_BASE + 0x4C) +#define DVFSRC_EMI_QOS2 (DVFSRC_BASE + 0x50) +#define DVFSRC_EMI_MD2SPM0 (DVFSRC_BASE + 0x54) +#define DVFSRC_EMI_MD2SPM1 (DVFSRC_BASE + 0x58) +#define DVFSRC_EMI_MD2SPM2 (DVFSRC_BASE + 0x5C) +#define DVFSRC_EMI_MD2SPM0_T (DVFSRC_BASE + 0x60) +#define DVFSRC_EMI_MD2SPM1_T (DVFSRC_BASE + 0x64) +#define DVFSRC_EMI_MD2SPM2_T (DVFSRC_BASE + 0x68) +#define DVFSRC_VCORE_REQUEST (DVFSRC_BASE + 0x6C) +#define DVFSRC_VCORE_REQUEST2 (DVFSRC_BASE + 0x70) +#define DVFSRC_VCORE_REQUEST3 (DVFSRC_BASE + 0x74) +#define DVFSRC_VCORE_REQUEST4 (DVFSRC_BASE + 0x78) +#define DVFSRC_VCORE_HRT (DVFSRC_BASE + 0x7C) +#define DVFSRC_VCORE_HRT2 (DVFSRC_BASE + 0x80) +#define DVFSRC_VCORE_HRT3 (DVFSRC_BASE + 0x84) +#define DVFSRC_VCORE_QOS0 (DVFSRC_BASE + 0x88) +#define DVFSRC_VCORE_QOS1 (DVFSRC_BASE + 0x8C) +#define DVFSRC_VCORE_QOS2 (DVFSRC_BASE + 0x90) +#define DVFSRC_VCORE_MD2SPM0 (DVFSRC_BASE + 0x94) +#define DVFSRC_VCORE_MD2SPM1 (DVFSRC_BASE + 0x98) +#define DVFSRC_VCORE_MD2SPM2 (DVFSRC_BASE + 0x9C) +#define DVFSRC_VCORE_MD2SPM0_T (DVFSRC_BASE + 0xA0) +#define DVFSRC_VCORE_MD2SPM1_T (DVFSRC_BASE + 0xA4) +#define DVFSRC_VCORE_MD2SPM2_T (DVFSRC_BASE + 0xA8) +#define DVFSRC_MD_VSRAM_REMAP (DVFSRC_BASE + 0xBC) +#define DVFSRC_HALT_SW_CONTROL (DVFSRC_BASE + 0xC0) +#define DVFSRC_INT (DVFSRC_BASE + 0xC4) +#define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8) +#define DVFSRC_INT_CLR (DVFSRC_BASE + 0xCC) +#define DVFSRC_BW_MON_WINDOW (DVFSRC_BASE + 0xD0) +#define DVFSRC_BW_MON_THRES_1 (DVFSRC_BASE + 0xD4) +#define DVFSRC_BW_MON_THRES_2 (DVFSRC_BASE + 0xD8) +#define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC) +#define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4) +#define DVFSRC_DEBOUNCE_FOUR (DVFSRC_BASE + 0xF0) +#define DVFSRC_DEBOUNCE_RISE_FALL (DVFSRC_BASE + 0xF4) +#define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8) +#define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100) +#define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104) +#define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108) +#define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x10C) +#define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x110) +#define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x114) +#define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x118) +#define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x11C) +#define DVFSRC_MM_BW_0 (DVFSRC_BASE + 0x200) +#define DVFSRC_MM_BW_1 (DVFSRC_BASE + 0x204) +#define DVFSRC_MM_BW_2 (DVFSRC_BASE + 0x208) +#define DVFSRC_MM_BW_3 (DVFSRC_BASE + 0x20C) +#define DVFSRC_MM_BW_4 (DVFSRC_BASE + 0x210) +#define DVFSRC_MM_BW_5 (DVFSRC_BASE + 0x214) +#define DVFSRC_MM_BW_6 (DVFSRC_BASE + 0x218) +#define DVFSRC_MM_BW_7 (DVFSRC_BASE + 0x21C) +#define DVFSRC_MM_BW_8 (DVFSRC_BASE + 0x220) +#define DVFSRC_MM_BW_9 (DVFSRC_BASE + 0x224) +#define DVFSRC_MM_BW_10 (DVFSRC_BASE + 0x228) +#define DVFSRC_MM_BW_11 (DVFSRC_BASE + 0x22C) +#define DVFSRC_MM_BW_12 (DVFSRC_BASE + 0x230) +#define DVFSRC_MM_BW_13 (DVFSRC_BASE + 0x234) +#define DVFSRC_MM_BW_14 (DVFSRC_BASE + 0x238) +#define DVFSRC_MM_BW_15 (DVFSRC_BASE + 0x23C) +#define DVFSRC_MD_BW_0 (DVFSRC_BASE + 0x240) +#define DVFSRC_MD_BW_1 (DVFSRC_BASE + 0x244) +#define DVFSRC_MD_BW_2 (DVFSRC_BASE + 0x248) +#define DVFSRC_MD_BW_3 (DVFSRC_BASE + 0x24C) +#define DVFSRC_MD_BW_4 (DVFSRC_BASE + 0x250) +#define DVFSRC_MD_BW_5 (DVFSRC_BASE + 0x254) +#define DVFSRC_MD_BW_6 (DVFSRC_BASE + 0x258) +#define DVFSRC_MD_BW_7 (DVFSRC_BASE + 0x25C) +#define DVFSRC_SW_BW_0 (DVFSRC_BASE + 0x260) +#define DVFSRC_SW_BW_1 (DVFSRC_BASE + 0x264) +#define DVFSRC_SW_BW_2 (DVFSRC_BASE + 0x268) +#define DVFSRC_SW_BW_3 (DVFSRC_BASE + 0x26C) +#define DVFSRC_SW_BW_4 (DVFSRC_BASE + 0x270) +#define DVFSRC_SW_BW_5 (DVFSRC_BASE + 0x274) +#define DVFSRC_SW_BW_6 (DVFSRC_BASE + 0x278) +#define DVFSRC_QOS_EN (DVFSRC_BASE + 0x280) +#define DVFSRC_MD_BW_URG (DVFSRC_BASE + 0x284) +#define DVFSRC_ISP_HRT (DVFSRC_BASE + 0x290) +#define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x294) +#define DVFSRC_SEC_SW_REQ (DVFSRC_BASE + 0x304) +#define DVFSRC_EMI_MON_DEBOUNCE_TIME (DVFSRC_BASE + 0x308) +#define DVFSRC_MD_LATENCY_IMPROVE (DVFSRC_BASE + 0x30C) +#define DVFSRC_BASIC_CONTROL_3 (DVFSRC_BASE + 0x310) +#define DVFSRC_DEBOUNCE_TIME (DVFSRC_BASE + 0x314) +#define DVFSRC_LEVEL_MASK (DVFSRC_BASE + 0x318) +#define DVFSRC_95MD_SCEN_EMI0 (DVFSRC_BASE + 0x500) +#define DVFSRC_95MD_SCEN_EMI1 (DVFSRC_BASE + 0x504) +#define DVFSRC_95MD_SCEN_EMI2 (DVFSRC_BASE + 0x508) +#define DVFSRC_95MD_SCEN_EMI3 (DVFSRC_BASE + 0x50C) +#define DVFSRC_95MD_SCEN_EMI0_T (DVFSRC_BASE + 0x510) +#define DVFSRC_95MD_SCEN_EMI1_T (DVFSRC_BASE + 0x514) +#define DVFSRC_95MD_SCEN_EMI2_T (DVFSRC_BASE + 0x518) +#define DVFSRC_95MD_SCEN_EMI3_T (DVFSRC_BASE + 0x51C) +#define DVFSRC_95MD_SCEN_EMI4 (DVFSRC_BASE + 0x520) +#define DVFSRC_95MD_SCEN_BW0 (DVFSRC_BASE + 0x524) +#define DVFSRC_95MD_SCEN_BW1 (DVFSRC_BASE + 0x528) +#define DVFSRC_95MD_SCEN_BW2 (DVFSRC_BASE + 0x52C) +#define DVFSRC_95MD_SCEN_BW3 (DVFSRC_BASE + 0x530) +#define DVFSRC_95MD_SCEN_BW0_T (DVFSRC_BASE + 0x534) +#define DVFSRC_95MD_SCEN_BW1_T (DVFSRC_BASE + 0x538) +#define DVFSRC_95MD_SCEN_BW2_T (DVFSRC_BASE + 0x53C) +#define DVFSRC_95MD_SCEN_BW3_T (DVFSRC_BASE + 0x540) +#define DVFSRC_95MD_SCEN_BW4 (DVFSRC_BASE + 0x544) +#define DVFSRC_MD_LEVEL_SW_REG (DVFSRC_BASE + 0x548) +#define DVFSRC_RSRV_0 (DVFSRC_BASE + 0x600) +#define DVFSRC_RSRV_1 (DVFSRC_BASE + 0x604) +#define DVFSRC_RSRV_2 (DVFSRC_BASE + 0x608) +#define DVFSRC_RSRV_3 (DVFSRC_BASE + 0x60C) +#define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610) +#define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x614) +#define DVFSRC_SPM_RESEND (DVFSRC_BASE + 0x630) +#define DVFSRC_DEBUG_STA_0 (DVFSRC_BASE + 0x700) +#define DVFSRC_DEBUG_STA_1 (DVFSRC_BASE + 0x704) +#define DVFSRC_DEBUG_STA_2 (DVFSRC_BASE + 0x708) +#define DVFSRC_DEBUG_STA_3 (DVFSRC_BASE + 0x70C) +#define DVFSRC_DEBUG_STA_4 (DVFSRC_BASE + 0x710) +#define DVFSRC_EMI_REQUEST7 (DVFSRC_BASE + 0x800) +#define DVFSRC_EMI_HRT_1 (DVFSRC_BASE + 0x804) +#define DVFSRC_EMI_HRT2_1 (DVFSRC_BASE + 0x808) +#define DVFSRC_EMI_HRT3_1 (DVFSRC_BASE + 0x80C) +#define DVFSRC_EMI_QOS3 (DVFSRC_BASE + 0x810) +#define DVFSRC_EMI_QOS4 (DVFSRC_BASE + 0x814) +#define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0xA00) +#define DVFSRC_DDR_REQUEST2 (DVFSRC_BASE + 0xA04) +#define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0xA08) +#define DVFSRC_DDR_REQUEST4 (DVFSRC_BASE + 0xA0C) +#define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0xA10) +#define DVFSRC_DDR_REQUEST6 (DVFSRC_BASE + 0xA14) +#define DVFSRC_DDR_REQUEST7 (DVFSRC_BASE + 0xA18) +#define DVFSRC_DDR_HRT (DVFSRC_BASE + 0xA1C) +#define DVFSRC_DDR_HRT2 (DVFSRC_BASE + 0xA20) +#define DVFSRC_DDR_HRT3 (DVFSRC_BASE + 0xA24) +#define DVFSRC_DDR_HRT_1 (DVFSRC_BASE + 0xA28) +#define DVFSRC_DDR_HRT2_1 (DVFSRC_BASE + 0xA2C) +#define DVFSRC_DDR_HRT3_1 (DVFSRC_BASE + 0xA30) +#define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0xA34) +#define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38) +#define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0xA3C) +#define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0xA40) +#define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0xA44) +#define DVFSRC_DDR_MD2SPM0 (DVFSRC_BASE + 0xA48) +#define DVFSRC_DDR_MD2SPM1 (DVFSRC_BASE + 0xA4C) +#define DVFSRC_DDR_MD2SPM2 (DVFSRC_BASE + 0xA50) +#define DVFSRC_DDR_MD2SPM0_T (DVFSRC_BASE + 0xA54) +#define DVFSRC_DDR_MD2SPM1_T (DVFSRC_BASE + 0xA58) +#define DVFSRC_DDR_MD2SPM2_T (DVFSRC_BASE + 0xA5C) +#define DVFSRC_HRT_REQ_UNIT (DVFSRC_BASE + 0xA60) +#define DVSFRC_HRT_REQ_MD_URG (DVFSRC_BASE + 0xA64) +#define DVFSRC_HRT_REQ_MD_BW_0 (DVFSRC_BASE + 0xA68) +#define DVFSRC_HRT_REQ_MD_BW_1 (DVFSRC_BASE + 0xA6C) +#define DVFSRC_HRT_REQ_MD_BW_2 (DVFSRC_BASE + 0xA70) +#define DVFSRC_HRT_REQ_MD_BW_3 (DVFSRC_BASE + 0xA74) +#define DVFSRC_HRT_REQ_MD_BW_4 (DVFSRC_BASE + 0xA78) +#define DVFSRC_HRT_REQ_MD_BW_5 (DVFSRC_BASE + 0xA7C) +#define DVFSRC_HRT_REQ_MD_BW_6 (DVFSRC_BASE + 0xA80) +#define DVFSRC_HRT_REQ_MD_BW_7 (DVFSRC_BASE + 0xA84) +#define DVFSRC_HRT1_REQ_MD_BW_0 (DVFSRC_BASE + 0xA88) +#define DVFSRC_HRT1_REQ_MD_BW_1 (DVFSRC_BASE + 0xA8C) +#define DVFSRC_HRT1_REQ_MD_BW_2 (DVFSRC_BASE + 0xA90) +#define DVFSRC_HRT1_REQ_MD_BW_3 (DVFSRC_BASE + 0xA94) +#define DVFSRC_HRT1_REQ_MD_BW_4 (DVFSRC_BASE + 0xA98) +#define DVFSRC_HRT1_REQ_MD_BW_5 (DVFSRC_BASE + 0xA9C) +#define DVFSRC_HRT1_REQ_MD_BW_6 (DVFSRC_BASE + 0xAA0) +#define DVFSRC_HRT1_REQ_MD_BW_7 (DVFSRC_BASE + 0xAA4) +#define DVFSRC_HRT_REQ_MD_BW_8 (DVFSRC_BASE + 0xAA8) +#define DVFSRC_HRT_REQ_MD_BW_9 (DVFSRC_BASE + 0xAAC) +#define DVFSRC_HRT_REQ_MD_BW_10 (DVFSRC_BASE + 0xAB0) +#define DVFSRC_HRT1_REQ_MD_BW_8 (DVFSRC_BASE + 0xAB4) +#define DVFSRC_HRT1_REQ_MD_BW_9 (DVFSRC_BASE + 0xAB8) +#define DVFSRC_HRT1_REQ_MD_BW_10 (DVFSRC_BASE + 0xABC) +#define DVFSRC_HRT_REQ_BW_SW_REG (DVFSRC_BASE + 0xAC0) +#define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0xAC4) +#define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0xAC8) +#define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0xACC) +#define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0xAD0) +#define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0xAD4) +#define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0xAD8) +#define DVFSRC_HRT_LOW (DVFSRC_BASE + 0xADC) +#define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0xAE0) +#define DVFSRC_LAST (DVFSRC_BASE + 0xAE4) +#define DVFSRC_LAST_L (DVFSRC_BASE + 0xAE8) +#define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0xAEC) +#define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0xAF0) +#define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0xAF4) +#define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8) +#define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0xAFC) +#define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0xB00) +#define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04) +#define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0xB08) +#define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0xB0C) +#define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0xBF0) +#define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0xBF4) +#define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0xBF8) +#define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0xBFC) +#define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0xC00) +#define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0xC04) +#define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0xC08) +#define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0xC0C) +#define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0xCF0) +#define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0xCF4) +#define DVFSRC_EMI_HRT_2 (DVFSRC_BASE + 0xCF8) +#define DVFSRC_EMI_HRT2_2 (DVFSRC_BASE + 0xCFC) +#define DVFSRC_EMI_HRT3_2 (DVFSRC_BASE + 0xD00) +#define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0xD04) +#define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0xD08) +#define DVFSRC_DDR_HRT_2 (DVFSRC_BASE + 0xD0C) +#define DVFSRC_DDR_HRT2_2 (DVFSRC_BASE + 0xD10) +#define DVFSRC_DDR_HRT3_2 (DVFSRC_BASE + 0xD14) +#define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18) +#define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0xD1C) +#define DVFSRC_VCORE_REQUEST5 (DVFSRC_BASE + 0xD20) +#define DVFSRC_VCORE_HRT_1 (DVFSRC_BASE + 0xD24) +#define DVFSRC_VCORE_HRT2_1 (DVFSRC_BASE + 0xD28) +#define DVFSRC_VCORE_HRT3_1 (DVFSRC_BASE + 0xD2C) +#define DVFSRC_VCORE_QOS3 (DVFSRC_BASE + 0xD30) +#define DVFSRC_VCORE_QOS4 (DVFSRC_BASE + 0xD34) +#define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0xD38) +#define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0xD3C) +#define DVFSRC_BASIC_CONTROL_2 (DVFSRC_BASE + 0xD40) +#define DVFSRC_CURRENT_LEVEL (DVFSRC_BASE + 0xD44) +#define DVFSRC_TARGET_LEVEL (DVFSRC_BASE + 0xD48) +#define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0xD4C) +#define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0xD50) +#define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0xD54) +#define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0xD58) +#define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0xD5C) +#define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0xD60) +#define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0xD64) +#define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0xD68) +#define DVFSRC_CURRENT_FORCE (DVFSRC_BASE + 0xD6C) +#define DVFSRC_TARGET_FORCE (DVFSRC_BASE + 0xD70) +#define DVFSRC_EMI_ADD_REQUEST (DVFSRC_BASE + 0xD74) + +#define VCORE_VB_EFUSE (0x11C105E8) + +#endif /* MT_SPM_VCOREFS_H */ diff --git a/plat/mediatek/mt8186/include/platform_def.h b/plat/mediatek/mt8186/include/platform_def.h index 90096e942..b8b877a6d 100644 --- a/plat/mediatek/mt8186/include/platform_def.h +++ b/plat/mediatek/mt8186/include/platform_def.h @@ -47,6 +47,7 @@ #define IOCFG_RB_BASE (IO_PHYS + 0x00002A00) #define IOCFG_RT_BASE (IO_PHYS + 0x00002C00) #define APMIXEDSYS (IO_PHYS + 0x0000C000) +#define DVFSRC_BASE (IO_PHYS + 0x00012000) #define MMSYS_BASE (IO_PHYS + 0x04000000) #define MDPSYS_BASE (IO_PHYS + 0x0B000000) diff --git a/plat/mediatek/mt8186/plat_sip_calls.c b/plat/mediatek/mt8186/plat_sip_calls.c index 716f3d9d8..87ba786fc 100644 --- a/plat/mediatek/mt8186/plat_sip_calls.c +++ b/plat/mediatek/mt8186/plat_sip_calls.c @@ -1,11 +1,14 @@ /* - * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include #include +#include +#include +#include "plat_sip_calls.h" uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid, u_register_t x1, @@ -16,7 +19,14 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid, void *handle, u_register_t flags) { + uint64_t ret; + switch (smc_fid) { + case MTK_SIP_VCORE_CONTROL_ARCH32: + case MTK_SIP_VCORE_CONTROL_ARCH64: + ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); + SMC_RET2(handle, ret, x4); + break; default: ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); break;