FVP: apply new naming conventions to memory regions
Secure ROM at address 0x0000_0000 is defined as FVP_TRUSTED_ROM Secure RAM at address 0x0400_0000 is defined as FVP_TRUSTED_SRAM Secure RAM at address 0x0600_0000 is defined as FVP_TRUSTED_DRAM BLn_BASE and BLn_LIMIT definitions have been updated and are based on these new memory regions. The available memory for each bootloader in the linker script is defined by BLn_BASE and BLn_LIMIT, instead of the complete memory region. TZROM_BASE/SIZE and TZRAM_BASE/SIZE are no longer required as part of the platform porting. FVP common definitions are defined in fvp_def.h while platform_def.h contains exclusively (with a few exceptions) the definitions that are mandatory in the porting guide. Therefore, platform_def.h now includes fvp_def.h instead of the other way around. Porting guide has been updated to reflect these changes. Change-Id: I39a6088eb611fc4a347db0db4b8f1f0417dbab05
This commit is contained in:
Juan Castillo
parent
c1efc4c066
commit
637ebd2eb9
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@ -35,8 +35,8 @@ OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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ENTRY(bl1_entrypoint)
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MEMORY {
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ROM (rx): ORIGIN = TZROM_BASE, LENGTH = TZROM_SIZE
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RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
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ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT
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RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT
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}
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SECTIONS
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@ -35,7 +35,7 @@ OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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ENTRY(bl2_entrypoint)
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MEMORY {
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RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
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RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT
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}
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@ -36,7 +36,7 @@ ENTRY(bl31_entrypoint)
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MEMORY {
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RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
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RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT
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}
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@ -150,31 +150,6 @@ file is found in [plat/fvp/include/platform_def.h].
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Defines the total number of nodes in the affinity heirarchy at all affinity
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levels used by the platform.
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* **#define : TZROM_BASE**
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Defines the base address of secure ROM on the platform, where the BL1 binary
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is loaded. This constant is used by the linker scripts to ensure that the
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BL1 image fits into the available memory.
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* **#define : TZROM_SIZE**
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Defines the size of secure ROM on the platform. This constant is used by the
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linker scripts to ensure that the BL1 image fits into the available memory.
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* **#define : TZRAM_BASE**
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Defines the base address of the secure RAM on platform, where the data
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section of the BL1 binary is loaded. The BL2 and BL3-1 images are also
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loaded in this secure RAM region. This constant is used by the linker
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scripts to ensure that the BL1 data section and BL2/BL3-1 binary images fit
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into the available memory.
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* **#define : TZRAM_SIZE**
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Defines the size of the secure RAM on the platform. This constant is used by
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the linker scripts to ensure that the BL1 data section and BL2/BL3-1 binary
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images fit into the available memory.
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* **#define : BL1_RO_BASE**
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Defines the base address in secure ROM where BL1 originally lives. Must be
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@ -314,11 +314,11 @@ The Firmware Package contains this new image:
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On FVP, the TSP binary runs from Trusted SRAM by default. It is also possible
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to run it from Trusted DRAM. This is controlled by the build configuration
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`TSP_RAM_LOCATION`:
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`FVP_TSP_RAM_LOCATION`:
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CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- \
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BL33=<path-to>/<bl33_image> \
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make PLAT=fvp SPD=tspd TSP_RAM_LOCATION=tdram all fip
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make PLAT=fvp SPD=tspd FVP_TSP_RAM_LOCATION=tdram all fip
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### Checking source code style
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@ -56,9 +56,9 @@ plat_config_t plat_config;
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* configure_mmu_elx() will give the available subset of that,
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*/
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const mmap_region_t fvp_mmap[] = {
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{ TZROM_BASE, TZROM_BASE, TZROM_SIZE,
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{ FVP_TRUSTED_ROM_BASE, FVP_TRUSTED_ROM_BASE, FVP_TRUSTED_ROM_SIZE,
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MT_MEMORY | MT_RO | MT_SECURE },
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{ TZDRAM_BASE, TZDRAM_BASE, TZDRAM_SIZE,
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{ FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE },
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{ FLASH0_BASE, FLASH0_BASE, FLASH0_SIZE,
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MT_MEMORY | MT_RO | MT_SECURE },
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@ -34,7 +34,7 @@
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#include <gic_v2.h>
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#include <pl011.h>
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#include "../drivers/pwrc/fvp_pwrc.h"
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#include "../fvp_def.h"
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#include "platform_def.h"
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.globl platform_get_entrypoint
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.globl plat_secondary_cold_boot_setup
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@ -140,7 +140,7 @@ warm_reset:
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* its safe to read it here with SO attributes
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* ---------------------------------------------
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*/
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ldr x10, =TZDRAM_BASE + MBOX_OFF
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ldr x10, =FVP_TRUSTED_DRAM_BASE + MBOX_OFF
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bl platform_get_core_pos
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lsl x0, x0, #CACHE_WRITEBACK_SHIFT
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ldr x0, [x10, x0]
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@ -163,7 +163,7 @@ _panic: b _panic
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* -----------------------------------------------------
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*/
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func platform_mem_init
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ldr x0, =TZDRAM_BASE + MBOX_OFF
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ldr x0, =FVP_TRUSTED_DRAM_BASE + MBOX_OFF
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mov w1, #PLATFORM_CORE_COUNT
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loop:
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str xzr, [x0], #CACHE_WRITEBACK_GRANULE
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@ -76,12 +76,12 @@ void bl1_early_platform_setup(void)
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console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_tzram_layout.total_base = TZRAM_BASE;
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bl1_tzram_layout.total_size = TZRAM_SIZE;
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bl1_tzram_layout.total_base = FVP_TRUSTED_SRAM_BASE;
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bl1_tzram_layout.total_size = FVP_TRUSTED_SRAM_SIZE;
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/* Calculate how much RAM BL1 is using and how much remains free */
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bl1_tzram_layout.free_base = TZRAM_BASE;
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bl1_tzram_layout.free_size = TZRAM_SIZE;
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bl1_tzram_layout.free_base = FVP_TRUSTED_SRAM_BASE;
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bl1_tzram_layout.free_size = FVP_TRUSTED_SRAM_SIZE;
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reserve_mem(&bl1_tzram_layout.free_base,
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&bl1_tzram_layout.free_size,
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BL1_RAM_BASE,
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@ -117,8 +117,8 @@ void bl1_plat_arch_setup(void)
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fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
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bl1_tzram_layout.total_size,
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TZROM_BASE,
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TZROM_BASE + TZROM_SIZE,
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BL1_RO_BASE,
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BL1_RO_LIMIT,
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BL1_COHERENT_RAM_BASE,
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BL1_COHERENT_RAM_LIMIT);
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}
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@ -97,7 +97,7 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
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{
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bl2_to_bl31_params_mem_t *bl31_params_mem;
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#if TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
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#if FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM
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/*
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* Ensure that the secure DRAM memory used for passing BL31 arguments
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* does not overlap with the BL32_BASE.
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@ -1,4 +1,4 @@
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#/*
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/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -31,19 +31,29 @@
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#ifndef __FVP_DEF_H__
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#define __FVP_DEF_H__
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#include <platform_def.h> /* for TZROM_SIZE */
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/* Firmware Image Package */
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#define FIP_IMAGE_NAME "fip.bin"
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#define FVP_PRIMARY_CPU 0x0
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/* Memory location options for Shared data and TSP in FVP */
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#define FVP_IN_TRUSTED_SRAM 0
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#define FVP_IN_TRUSTED_DRAM 1
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/*******************************************************************************
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* FVP memory map related constants
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******************************************************************************/
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#define FVP_TRUSTED_ROM_BASE 0x00000000
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#define FVP_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
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#define FVP_TRUSTED_SRAM_BASE 0x04000000
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#define FVP_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
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#define FVP_TRUSTED_DRAM_BASE 0x06000000
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#define FVP_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
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#define FLASH0_BASE 0x08000000
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#define FLASH0_SIZE TZROM_SIZE
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#define FLASH0_SIZE 0x04000000
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#define FLASH1_BASE 0x0c000000
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#define FLASH1_SIZE 0x04000000
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@ -67,7 +77,7 @@
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#define MBOX_OFF 0x1000
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/* Base address where parameters to BL31 are stored */
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#define PARAMS_BASE TZDRAM_BASE
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#define PARAMS_BASE FVP_TRUSTED_DRAM_BASE
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#define DRAM1_BASE 0x80000000ull
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#define DRAM1_SIZE 0x80000000ull
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@ -229,5 +239,4 @@
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#define FVP_NSAID_HDLCD0 2
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#define FVP_NSAID_CLCD 7
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#endif /* __FVP_DEF_H__ */
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@ -103,7 +103,7 @@ int fvp_affinst_on(unsigned long mpidr,
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} while (psysr & PSYSR_AFF_L0);
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linear_id = platform_get_core_pos(mpidr);
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fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
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fvp_mboxes = (mailbox_t *) (FVP_TRUSTED_DRAM_BASE + MBOX_OFF);
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fvp_mboxes[linear_id].value = sec_entrypoint;
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flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
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sizeof(unsigned long));
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@ -240,7 +240,8 @@ int fvp_affinst_suspend(unsigned long mpidr,
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/* Program the jump address for the target cpu */
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linear_id = platform_get_core_pos(mpidr);
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fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
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fvp_mboxes = (mailbox_t *) (FVP_TRUSTED_DRAM_BASE +
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MBOX_OFF);
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fvp_mboxes[linear_id].value = sec_entrypoint;
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flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
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sizeof(unsigned long));
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@ -329,7 +330,8 @@ int fvp_affinst_on_finish(unsigned long mpidr,
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fvp_pwrc_clr_wen(mpidr);
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/* Zero the jump address in the mailbox for this cpu */
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fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
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fvp_mboxes = (mailbox_t *) (FVP_TRUSTED_DRAM_BASE +
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MBOX_OFF);
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linear_id = platform_get_core_pos(mpidr);
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fvp_mboxes[linear_id].value = 0;
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flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
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@ -32,6 +32,7 @@
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include <../fvp_def.h>
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/*******************************************************************************
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@ -73,32 +74,23 @@
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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#define TZROM_BASE 0x00000000
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#define TZROM_SIZE 0x04000000
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#define TZRAM_BASE 0x04000000
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#define TZRAM_SIZE 0x40000
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/* Location of trusted dram on the base fvp */
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#define TZDRAM_BASE 0x06000000
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#define TZDRAM_SIZE 0x02000000
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/*******************************************************************************
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* BL1 specific defines.
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* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
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* addresses.
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******************************************************************************/
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#define BL1_RO_BASE TZROM_BASE
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#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE)
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#define BL1_RO_BASE FVP_TRUSTED_ROM_BASE
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#define BL1_RO_LIMIT (FVP_TRUSTED_ROM_BASE \
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+ FVP_TRUSTED_ROM_SIZE)
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/*
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* Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
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* the current BL1 RW debug size plus a little space for growth.
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*/
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#define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x6000)
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#define BL1_RW_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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#define BL1_RW_BASE (FVP_TRUSTED_SRAM_BASE + \
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FVP_TRUSTED_SRAM_SIZE - \
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0x6000)
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#define BL1_RW_LIMIT (FVP_TRUSTED_SRAM_BASE + \
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FVP_TRUSTED_SRAM_SIZE)
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/*******************************************************************************
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* BL2 specific defines.
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@ -117,9 +109,12 @@
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* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
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* current BL3-1 debug size plus a little space for growth.
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*/
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#define BL31_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1D000)
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#define BL31_BASE (FVP_TRUSTED_SRAM_BASE + \
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FVP_TRUSTED_SRAM_SIZE - \
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0x1D000)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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#define BL31_LIMIT (FVP_TRUSTED_SRAM_BASE + \
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FVP_TRUSTED_SRAM_SIZE)
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/*******************************************************************************
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* BL32 specific defines.
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@ -127,22 +122,19 @@
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/*
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* On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
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*/
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#define TSP_IN_TZRAM 0
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#define TSP_IN_TZDRAM 1
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#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
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# define TSP_SEC_MEM_BASE TZRAM_BASE
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# define TSP_SEC_MEM_SIZE TZRAM_SIZE
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# define BL32_BASE TZRAM_BASE
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#if FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_SRAM
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# define TSP_SEC_MEM_BASE FVP_TRUSTED_SRAM_BASE
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# define TSP_SEC_MEM_SIZE FVP_TRUSTED_SRAM_SIZE
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# define BL32_BASE FVP_TRUSTED_SRAM_BASE
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# define BL32_PROGBITS_LIMIT BL2_BASE
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# define BL32_LIMIT BL31_BASE
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#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
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# define TSP_SEC_MEM_BASE TZDRAM_BASE
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# define TSP_SEC_MEM_SIZE TZDRAM_SIZE
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# define BL32_BASE (TZDRAM_BASE + 0x2000)
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# define BL32_LIMIT (TZDRAM_BASE + (1 << 21))
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#elif FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM
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# define TSP_SEC_MEM_BASE FVP_TRUSTED_DRAM_BASE
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# define TSP_SEC_MEM_SIZE FVP_TRUSTED_DRAM_SIZE
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# define BL32_BASE (FVP_TRUSTED_DRAM_BASE + 0x2000)
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# define BL32_LIMIT (FVP_TRUSTED_DRAM_BASE + (1 << 21))
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#else
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# error "Unsupported TSP_RAM_LOCATION_ID value"
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# error "Unsupported FVP_TSP_RAM_LOCATION_ID value"
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#endif
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/*******************************************************************************
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@ -30,18 +30,17 @@
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# On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
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# Trusted SRAM is the default.
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TSP_RAM_LOCATION := tsram
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ifeq (${TSP_RAM_LOCATION}, tsram)
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TSP_RAM_LOCATION_ID := TSP_IN_TZRAM
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else ifeq (${TSP_RAM_LOCATION}, tdram)
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TSP_RAM_LOCATION_ID := TSP_IN_TZDRAM
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FVP_TSP_RAM_LOCATION := tsram
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ifeq (${FVP_TSP_RAM_LOCATION}, tsram)
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FVP_TSP_RAM_LOCATION_ID := FVP_IN_TRUSTED_SRAM
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else ifeq (${FVP_TSP_RAM_LOCATION}, tdram)
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FVP_TSP_RAM_LOCATION_ID := FVP_IN_TRUSTED_DRAM
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else
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$(error "Unsupported TSP_RAM_LOCATION value")
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$(error "Unsupported FVP_TSP_RAM_LOCATION value")
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endif
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# Process TSP_RAM_LOCATION_ID flag
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$(eval $(call add_define,TSP_RAM_LOCATION_ID))
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# Process flags
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$(eval $(call add_define,FVP_TSP_RAM_LOCATION_ID))
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PLAT_INCLUDES := -Iplat/fvp/include/
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