Merge "plat/arm: Re-enable PIE when RESET_TO_BL31=1" into integration
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commit
63b9627190
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@ -403,21 +403,16 @@
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#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
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#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
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PLAT_ARM_MAX_BL31_SIZE)
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PLAT_ARM_MAX_BL31_SIZE)
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#elif (RESET_TO_BL31)
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#elif (RESET_TO_BL31)
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/* Ensure Position Independent support (PIE) is enabled for this config.*/
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# if ENABLE_PIE
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# if !ENABLE_PIE
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# error "BL31 must be a PIE if RESET_TO_BL31=1."
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#endif
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/*
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/*
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* Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
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* Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
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* used for building BL31 and not used for loading BL31.
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* used for building BL31 and not used for loading BL31.
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*/
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*/
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# define BL31_BASE 0x0
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# define BL31_BASE 0x0
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# define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE
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# define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE
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# else
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/* Put BL31_BASE in the middle of the Trusted SRAM.*/
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# define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \
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(PLAT_ARM_TRUSTED_SRAM_SIZE >> 1))
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# define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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# endif /* ENABLE_PIE */
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#else
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#else
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/* Put BL31 below BL2 in the Trusted SRAM.*/
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/* Put BL31 below BL2 in the Trusted SRAM.*/
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#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
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#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
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@ -244,15 +244,10 @@ ENABLE_AMU := 1
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# Enable dynamic mitigation support by default
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# Enable dynamic mitigation support by default
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DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
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DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
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# Enable reclaiming of BL31 initialisation code for secondary cores
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# stacks for FVP.
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ifneq (${RESET_TO_BL31},1)
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ifneq (${RESET_TO_BL31},1)
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# Enable reclaiming of BL31 initialisation code for secondary cores stacks for
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# FVP. We cannot enable PIE for this case because the overlayed init section
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# creates some dynamic relocations which cannot be handled by the fixup
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# logic currently.
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RECLAIM_INIT_CODE := 1
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RECLAIM_INIT_CODE := 1
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else
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# Enable PIE support when RESET_TO_BL31=1
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ENABLE_PIE := 1
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endif
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endif
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ifeq (${ENABLE_AMU},1)
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ifeq (${ENABLE_AMU},1)
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@ -130,6 +130,11 @@ ARM_CRYPTOCELL_INTEG := 0
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$(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG))
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$(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG))
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$(eval $(call add_define,ARM_CRYPTOCELL_INTEG))
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$(eval $(call add_define,ARM_CRYPTOCELL_INTEG))
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# Enable PIE support for RESET_TO_BL31 case
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ifeq (${RESET_TO_BL31},1)
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ENABLE_PIE := 1
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endif
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# CryptoCell integration relies on coherent buffers for passing data from
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# CryptoCell integration relies on coherent buffers for passing data from
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# the AP CPU to the CryptoCell
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# the AP CPU to the CryptoCell
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ifeq (${ARM_CRYPTOCELL_INTEG},1)
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ifeq (${ARM_CRYPTOCELL_INTEG},1)
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