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Add cache flush after BL1 writes heap info to DTB 

A cache flush is added in BL1, in Mbed TLS shared heap code. Thus, we
ensure that the heap info written to the DTB always gets written back to
memory.  Hence, sharing this info with other images is guaranteed.

Change-Id: I0faada31fe7a83854cd5e2cf277ba519e3f050d5
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
This commit is contained in:
John Tsichritzis 2018-09-07 10:52:12 +01:00
parent a606031e7c
commit 63cc265886
1 changed files with 11 additions and 1 deletions
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12
plat/arm/common/arm_dyn_cfg.c
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@ -21,6 +21,7 @@
/* Variable to store the address of TB_FW_CONFIG file */
static void *tb_fw_cfg_dtb;
static size_t tb_fw_cfg_dtb_size;
#if TRUSTED_BOARD_BOOT
@ -105,6 +106,13 @@ void arm_bl1_set_mbedtls_heap(void)
ERROR("BL1: unable to write shared Mbed TLS heap information to DTB\n");
panic();
}
/*
* Ensure that the info written to the DTB is visible to other
* images. It's critical because BL2 won't be able to proceed
* without the heap info.
*/
flush_dcache_range((uintptr_t)tb_fw_cfg_dtb,
tb_fw_cfg_dtb_size);
}
}
@ -125,7 +133,8 @@ void arm_load_tb_fw_config(void)
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_2, image_info_t, 0),
.image_info.image_base = ARM_TB_FW_CONFIG_BASE,
.image_info.image_max_size = ARM_TB_FW_CONFIG_LIMIT - ARM_TB_FW_CONFIG_BASE,
.image_info.image_max_size =
ARM_TB_FW_CONFIG_LIMIT - ARM_TB_FW_CONFIG_BASE
};
VERBOSE("BL1: Loading TB_FW_CONFIG\n");
@ -139,6 +148,7 @@ void arm_load_tb_fw_config(void)
/* At this point we know that a DTB is indeed available */
config_base = arm_tb_fw_info.image_info.image_base;
tb_fw_cfg_dtb = (void *)config_base;
tb_fw_cfg_dtb_size = (size_t)arm_tb_fw_info.image_info.image_max_size;
/* The BL2 ep_info arg0 is modified to point to TB_FW_CONFIG */
image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);