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Merge pull request #1839 from loumay-arm/lm/a7x_errata 

Cortex-A73/75/76 errata workaround
This commit is contained in:
Antonio Niño Díaz 2019-02-28 10:19:24 +00:00 committed by GitHub
parent 1baa28bb2d 5c6aa01aff
commit 64503b2f81
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GPG Key ID: 4AEE18F83AFDEB23
9 changed files with 326 additions and 4 deletions
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24
docs/cpu-specific-build-macros.rst
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@ -132,6 +132,30 @@ For Cortex-A72, the following errata build flags are defined :
- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
For Cortex-A73, the following errata build flags are defined :
- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
For Cortex-A75, the following errata build flags are defined :
- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
CPU. This needs to be enabled only for revision r0p0 of the CPU.
- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
CPU. This needs to be enabled only for revision r0p0 of the CPU.
For Cortex-A76, the following errata build flags are defined :
- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
DSU Errata Workarounds
----------------------

1
include/arch/aarch64/arch.h
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@ -251,6 +251,7 @@
#define SCTLR_NTWE_BIT (ULL(1) << 18)
#define SCTLR_WXN_BIT (ULL(1) << 19)
#define SCTLR_UWXN_BIT (ULL(1) << 20)
#define SCTLR_IESB_BIT (ULL(1) << 21)
#define SCTLR_E0E_BIT (ULL(1) << 24)
#define SCTLR_EE_BIT (ULL(1) << 25)
#define SCTLR_UCI_BIT (ULL(1) << 26)

2
include/lib/cpus/aarch64/cortex_a73.h
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@ -31,4 +31,6 @@
#define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3)
#define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2
#endif /* CORTEX_A73_H */

6
include/lib/cpus/aarch64/cortex_a76.h
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@ -18,9 +18,15 @@
#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0
#define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6)
#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)

45
lib/cpus/aarch64/cortex_a73.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -35,7 +35,47 @@ func cortex_a73_disable_smp
ret
endfunc cortex_a73_disable_smp
/* ---------------------------------------------------
* Errata Workaround for Cortex A73 Errata #855423.
* This applies only to revision <= r0p1 of Cortex A73.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* ---------------------------------------------------
*/
func errata_a73_855423_wa
/*
* Compare x0 against revision r0p1
*/
mov x17, x30
bl check_errata_855423
cbz x0, 1f
mrs x1, CORTEX_A73_IMP_DEF_REG2
orr x1, x1, #(1 << 7)
msr CORTEX_A73_IMP_DEF_REG2, x1
isb
1:
ret x17
endfunc errata_a73_855423_wa
func check_errata_855423
mov x1, #0x01
b cpu_rev_var_ls
endfunc check_errata_855423
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A73.
* -------------------------------------------------
*/
func cortex_a73_reset_func
mov x19, x30
bl cpu_get_rev_var
#if ERRATA_A73_855423
bl errata_a73_855423_wa
#endif
#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
cpu_check_csv2 x0, 1f
adr x0, wa_cve_2017_5715_bpiall_vbar
@ -60,7 +100,7 @@ func cortex_a73_reset_func
orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
msr CORTEX_A73_CPUECTLR_EL1, x0
isb
ret
ret x19
endfunc cortex_a73_reset_func
func cortex_a73_core_pwr_dwn
@ -160,6 +200,7 @@ func cortex_a73_errata_report
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A73_855423, cortex_a73, 855423
report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715
report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639

77
lib/cpus/aarch64/cortex_a75.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,8 +10,81 @@
#include <cpuamu.h>
#include <cpu_macros.S>
/* --------------------------------------------------
* Errata Workaround for Cortex A75 Errata #764081.
* This applies only to revision r0p0 of Cortex A75.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a75_764081_wa
/*
* Compare x0 against revision r0p0
*/
mov x17, x30
bl check_errata_764081
cbz x0, 1f
mrs x1, sctlr_el3
orr x1, x1 ,#SCTLR_IESB_BIT
msr sctlr_el3, x1
isb
1:
ret x17
endfunc errata_a75_764081_wa
func check_errata_764081
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_764081
/* --------------------------------------------------
* Errata Workaround for Cortex A75 Errata #790748.
* This applies only to revision r0p0 of Cortex A75.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a75_790748_wa
/*
* Compare x0 against revision r0p0
*/
mov x17, x30
bl check_errata_790748
cbz x0, 1f
mrs x1, CORTEX_A75_CPUACTLR_EL1
orr x1, x1 ,#(1 << 13)
msr CORTEX_A75_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a75_790748_wa
func check_errata_790748
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_790748
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A75.
* -------------------------------------------------
*/
func cortex_a75_reset_func
mov x19, x30
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_A75_764081
mov x0, x18
bl errata_a75_764081_wa
#endif
#if ERRATA_A75_790748
mov x0, x18
bl errata_a75_790748_wa
#endif
#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
cpu_check_csv2 x0, 1f
adr x0, wa_cve_2017_5715_bpiall_vbar
@ -109,6 +182,8 @@ func cortex_a75_errata_report
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A75_764081, cortex_a75, 764081
report_errata ERRATA_A75_790748, cortex_a75, 790748
report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715
report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639
report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184

111
lib/cpus/aarch64/cortex_a76.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -189,6 +189,90 @@ vector_entry cortex_a76_serror_aarch32
b serror_aarch32
end_vector_entry cortex_a76_serror_aarch32
/* --------------------------------------------------
* Errata Workaround for Cortex A76 Errata #1073348.
* This applies only to revision <= r1p0 of Cortex A76.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a76_1073348_wa
/*
* Compare x0 against revision r1p0
*/
mov x17, x30
bl check_errata_1073348
cbz x0, 1f
mrs x1, CORTEX_A76_CPUACTLR_EL1
orr x1, x1 ,#CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION
msr CORTEX_A76_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a76_1073348_wa
func check_errata_1073348
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_1073348
/* --------------------------------------------------
* Errata Workaround for Cortex A76 Errata #1130799.
* This applies only to revision <= r2p0 of Cortex A76.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a76_1130799_wa
/*
* Compare x0 against revision r2p0
*/
mov x17, x30
bl check_errata_1130799
cbz x0, 1f
mrs x1, CORTEX_A76_CPUACTLR2_EL1
orr x1, x1 ,#(1 << 59)
msr CORTEX_A76_CPUACTLR2_EL1, x1
isb
1:
ret x17
endfunc errata_a76_1130799_wa
func check_errata_1130799
mov x1, #0x20
b cpu_rev_var_ls
endfunc check_errata_1130799
/* --------------------------------------------------
* Errata Workaround for Cortex A76 Errata #1220197.
* This applies only to revision <= r2p0 of Cortex A76.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a76_1220197_wa
/*
* Compare x0 against revision r2p0
*/
mov x17, x30
bl check_errata_1220197
cbz x0, 1f
mrs x1, CORTEX_A76_CPUECTLR_EL1
orr x1, x1, #CORTEX_A76_CPUECTLR_EL1_WS_THR_L2
msr CORTEX_A76_CPUECTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a76_1220197_wa
func check_errata_1220197
mov x1, #0x20
b cpu_rev_var_ls
endfunc check_errata_1220197
func check_errata_cve_2018_3639
#if WORKAROUND_CVE_2018_3639
mov x0, #ERRATA_APPLIES
@ -206,8 +290,30 @@ func cortex_a76_disable_wa_cve_2018_3639
ret
endfunc cortex_a76_disable_wa_cve_2018_3639
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A76.
* Shall clobber: x0-x19
* -------------------------------------------------
*/
func cortex_a76_reset_func
mov x19, x30
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_A76_1073348
mov x0, x18
bl errata_a76_1073348_wa
#endif
#if ERRATA_A76_1130799
mov x0, x18
bl errata_a76_1130799_wa
#endif
#if ERRATA_A76_1220197
mov x0, x18
bl errata_a76_1220197_wa
#endif
#if WORKAROUND_CVE_2018_3639
/* If the PE implements SSBS, we don't need the dynamic workaround */
@ -271,6 +377,9 @@ func cortex_a76_errata_report
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A76_1073348, cortex_a76, 1073348
report_errata ERRATA_A76_1130799, cortex_a76, 1130799
report_errata ERRATA_A76_1220197, cortex_a76, 1220197
report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184

48
lib/cpus/cpu-ops.mk
View File

@ -119,6 +119,30 @@ ERRATA_A57_859972 ?=0
# only to revision <= r0p3 of the Cortex A72 cpu.
ERRATA_A72_859971 ?=0
# Flag to apply erratum 855423 workaround during reset. This erratum applies
# only to revision <= r0p1 of the Cortex A73 cpu.
ERRATA_A73_855423 ?=0
# Flag to apply erratum 764081 workaround during reset. This erratum applies
# only to revision <= r0p0 of the Cortex A75 cpu.
ERRATA_A75_764081 ?=0
# Flag to apply erratum 790748 workaround during reset. This erratum applies
# only to revision <= r0p0 of the Cortex A75 cpu.
ERRATA_A75_790748 ?=0
# Flag to apply erratum 1073348 workaround during reset. This erratum applies
# only to revision <= r1p0 of the Cortex A76 cpu.
ERRATA_A76_1073348 ?=0
# Flag to apply erratum 1130799 workaround during reset. This erratum applies
# only to revision <= r2p0 of the Cortex A76 cpu.
ERRATA_A76_1130799 ?=0
# Flag to apply erratum 1220197 workaround during reset. This erratum applies
# only to revision <= r2p0 of the Cortex A76 cpu.
ERRATA_A76_1220197 ?=0
# Flag to apply T32 CLREX workaround during reset. This erratum applies
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
ERRATA_N1_1043202 ?=1
@ -188,6 +212,30 @@ $(eval $(call add_define,ERRATA_A57_859972))
$(eval $(call assert_boolean,ERRATA_A72_859971))
$(eval $(call add_define,ERRATA_A72_859971))
# Process ERRATA_A73_855423 flag
$(eval $(call assert_boolean,ERRATA_A73_855423))
$(eval $(call add_define,ERRATA_A73_855423))
# Process ERRATA_A75_764081 flag
$(eval $(call assert_boolean,ERRATA_A75_764081))
$(eval $(call add_define,ERRATA_A75_764081))
# Process ERRATA_A75_790748 flag
$(eval $(call assert_boolean,ERRATA_A75_790748))
$(eval $(call add_define,ERRATA_A75_790748))
# Process ERRATA_A76_1073348 flag
$(eval $(call assert_boolean,ERRATA_A76_1073348))
$(eval $(call add_define,ERRATA_A76_1073348))
# Process ERRATA_A76_1130799 flag
$(eval $(call assert_boolean,ERRATA_A76_1130799))
$(eval $(call add_define,ERRATA_A76_1130799))
# Process ERRATA_A76_1220197 flag
$(eval $(call assert_boolean,ERRATA_A76_1220197))
$(eval $(call add_define,ERRATA_A76_1220197))
# Process ERRATA_N1_1043202 flag
$(eval $(call assert_boolean,ERRATA_N1_1043202))
$(eval $(call add_define,ERRATA_N1_1043202))

16
lib/el3_runtime/aarch64/context_mgmt.c
View File

@ -187,6 +187,14 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
| SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
}
#if ERRATA_A75_764081
/*
* If workaround of errata 764081 for Cortex-A75 is used then set
* SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
*/
sctlr_elx |= SCTLR_IESB_BIT;
#endif
/*
* Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
* and other EL2 registers are set up by cm_prepare_ns_entry() as they
@ -319,6 +327,14 @@ void cm_prepare_el3_exit(uint32_t security_state)
CTX_SCTLR_EL1);
sctlr_elx &= SCTLR_EE_BIT;
sctlr_elx |= SCTLR_EL2_RES1;
#if ERRATA_A75_764081
/*
* If workaround of errata 764081 for Cortex-A75 is used
* then set SCTLR_EL2.IESB to enable Implicit Error
* Synchronization Barrier.
*/
sctlr_elx |= SCTLR_IESB_BIT;
#endif
write_sctlr_el2(sctlr_elx);
} else if (el_implemented(2) != EL_IMPL_NONE) {
el2_unused = true;