Tegra: gpcdma: driver for general purpose DMA
This patch adds the driver for the general purpose DMA hardware block on newer Tegra SoCs. The GPCDMA is a special purpose DMA used to speed up memory copy operations to/from DRAM and TZSRAM. This patch introduces a macro 'USE_GPC_DMA' to allow platforms to override CPU based memory operations. Change-Id: I3170d409c83b77e785437b1002a8d70188fabbeb Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <delay_timer.h>
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#include <errno.h>
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#include <gpcdma.h>
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#include <mmio.h>
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#include <platform_def.h>
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#include <stdbool.h>
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#include <tegra_def.h>
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#include <utils_def.h>
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/* DMA channel registers */
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#define DMA_CH_CSR U(0x0)
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#define DMA_CH_CSR_WEIGHT_SHIFT U(10)
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#define DMA_CH_CSR_XFER_MODE_SHIFT U(21)
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#define DMA_CH_CSR_DMA_MODE_MEM2MEM U(4)
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#define DMA_CH_CSR_DMA_MODE_FIXEDPATTERN U(6)
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#define DMA_CH_CSR_IRQ_MASK_ENABLE (U(1) << 15)
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#define DMA_CH_CSR_RUN_ONCE (U(1) << 27)
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#define DMA_CH_CSR_ENABLE (U(1) << 31)
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#define DMA_CH_STAT U(0x4)
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#define DMA_CH_STAT_BUSY (U(1) << 31)
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#define DMA_CH_SRC_PTR U(0xC)
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#define DMA_CH_DST_PTR U(0x10)
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#define DMA_CH_HI_ADR_PTR U(0x14)
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#define DMA_CH_HI_ADR_PTR_SRC_MASK U(0xFF)
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#define DMA_CH_HI_ADR_PTR_DST_SHIFT U(16)
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#define DMA_CH_HI_ADR_PTR_DST_MASK U(0xFF)
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#define DMA_CH_MC_SEQ U(0x18)
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#define DMA_CH_MC_SEQ_REQ_CNT_SHIFT U(25)
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#define DMA_CH_MC_SEQ_REQ_CNT_VAL U(0x10)
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#define DMA_CH_MC_SEQ_BURST_SHIFT U(23)
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#define DMA_CH_MC_SEQ_BURST_16_WORDS U(0x3)
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#define DMA_CH_WORD_COUNT U(0x20)
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#define DMA_CH_FIXED_PATTERN U(0x34)
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#define DMA_CH_TZ U(0x38)
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#define DMA_CH_TZ_ACCESS_ENABLE U(0)
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#define DMA_CH_TZ_ACCESS_DISABLE U(3)
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#define MAX_TRANSFER_SIZE (1U*1024U*1024U*1024U) /* 1GB */
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#define GPCDMA_TIMEOUT_MS U(100)
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#define GPCDMA_RESET_BIT (U(1) << 1)
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static bool init_done;
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static void tegra_gpcdma_write32(uint32_t offset, uint32_t val)
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{
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mmio_write_32(TEGRA_GPCDMA_BASE + offset, val);
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}
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static uint32_t tegra_gpcdma_read32(uint32_t offset)
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{
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return mmio_read_32(TEGRA_GPCDMA_BASE + offset);
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}
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static void tegra_gpcdma_init(void)
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{
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/* assert reset for DMA engine */
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mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPCDMA_RST_SET_REG_OFFSET,
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GPCDMA_RESET_BIT);
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udelay(2);
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/* de-assert reset for DMA engine */
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mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPCDMA_RST_CLR_REG_OFFSET,
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GPCDMA_RESET_BIT);
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}
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static void tegra_gpcdma_memcpy_priv(uint64_t dst_addr, uint64_t src_addr,
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uint32_t num_bytes, uint32_t mode)
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{
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uint32_t val, timeout = 0;
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int32_t ret = 0;
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/* sanity check byte count */
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if ((num_bytes > MAX_TRANSFER_SIZE) || ((num_bytes & 0x3U) != U(0))) {
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ret = -EINVAL;
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}
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/* initialise GPCDMA block */
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if (!init_done) {
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tegra_gpcdma_init();
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init_done = true;
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}
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/* make sure channel isn't busy */
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val = tegra_gpcdma_read32(DMA_CH_STAT);
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if ((val & DMA_CH_STAT_BUSY) == DMA_CH_STAT_BUSY) {
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ERROR("DMA channel is busy\n");
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ret = -EBUSY;
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}
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if (ret == 0) {
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/* disable any DMA transfers */
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tegra_gpcdma_write32(DMA_CH_CSR, 0);
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/* enable DMA access to TZDRAM */
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tegra_gpcdma_write32(DMA_CH_TZ, DMA_CH_TZ_ACCESS_ENABLE);
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/* configure MC sequencer */
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val = (DMA_CH_MC_SEQ_REQ_CNT_VAL << DMA_CH_MC_SEQ_REQ_CNT_SHIFT) |
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(DMA_CH_MC_SEQ_BURST_16_WORDS << DMA_CH_MC_SEQ_BURST_SHIFT);
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tegra_gpcdma_write32(DMA_CH_MC_SEQ, val);
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/* reset fixed pattern */
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tegra_gpcdma_write32(DMA_CH_FIXED_PATTERN, 0);
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/* populate src and dst address registers */
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tegra_gpcdma_write32(DMA_CH_SRC_PTR, (uint32_t)src_addr);
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tegra_gpcdma_write32(DMA_CH_DST_PTR, (uint32_t)dst_addr);
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val = (uint32_t)((src_addr >> 32) & DMA_CH_HI_ADR_PTR_SRC_MASK);
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val |= (uint32_t)(((dst_addr >> 32) & DMA_CH_HI_ADR_PTR_DST_MASK) <<
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DMA_CH_HI_ADR_PTR_DST_SHIFT);
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tegra_gpcdma_write32(DMA_CH_HI_ADR_PTR, val);
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/* transfer size (in words) */
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tegra_gpcdma_write32(DMA_CH_WORD_COUNT, ((num_bytes >> 2) - 1U));
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/* populate value for CSR */
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val = (mode << DMA_CH_CSR_XFER_MODE_SHIFT) |
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DMA_CH_CSR_RUN_ONCE | (U(1) << DMA_CH_CSR_WEIGHT_SHIFT) |
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DMA_CH_CSR_IRQ_MASK_ENABLE;
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tegra_gpcdma_write32(DMA_CH_CSR, val);
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/* enable transfer */
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val = tegra_gpcdma_read32(DMA_CH_CSR);
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val |= DMA_CH_CSR_ENABLE;
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tegra_gpcdma_write32(DMA_CH_CSR, val);
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/* wait till transfer completes */
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do {
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/* read the status */
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val = tegra_gpcdma_read32(DMA_CH_STAT);
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if ((val & DMA_CH_STAT_BUSY) != DMA_CH_STAT_BUSY) {
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break;
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}
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mdelay(1);
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timeout++;
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} while (timeout < GPCDMA_TIMEOUT_MS);
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/* flag timeout error */
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if (timeout == GPCDMA_TIMEOUT_MS) {
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ERROR("DMA transfer timed out\n");
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}
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dsbsy();
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/* disable DMA access to TZDRAM */
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tegra_gpcdma_write32(DMA_CH_TZ, DMA_CH_TZ_ACCESS_DISABLE);
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isb();
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}
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}
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/*******************************************************************************
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* Memcpy using GPCDMA block (Mem2Mem copy)
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******************************************************************************/
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void tegra_gpcdma_memcpy(uint64_t dst_addr, uint64_t src_addr,
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uint32_t num_bytes)
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{
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tegra_gpcdma_memcpy_priv(dst_addr, src_addr, num_bytes,
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DMA_CH_CSR_DMA_MODE_MEM2MEM);
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}
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/*******************************************************************************
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* Memset using GPCDMA block (Fixed pattern write)
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******************************************************************************/
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void tegra_gpcdma_zeromem(uint64_t dst_addr, uint32_t num_bytes)
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{
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tegra_gpcdma_memcpy_priv(dst_addr, 0, num_bytes,
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DMA_CH_CSR_DMA_MODE_FIXEDPATTERN);
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}
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __GPCDMA_H__
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#define __GPCDMA_H__
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#include <stdint.h>
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void tegra_gpcdma_memcpy(uint64_t dst_addr, uint64_t src_addr,
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uint32_t num_bytes);
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void tegra_gpcdma_zeromem(uint64_t dst_addr, uint32_t num_bytes);
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#endif /* __GPCDMA_H__ */
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#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (U(0x3) << 11)
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#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (U(0) << 11)
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/*******************************************************************************
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* Tegra General Purpose Centralised DMA constants
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******************************************************************************/
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#define TEGRA_GPCDMA_BASE U(0x2610000)
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/*******************************************************************************
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* Tegra Memory Controller constants
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******************************************************************************/
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#define TEGRA_CAR_RESET_BASE U(0x05000000)
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#define TEGRA_GPU_RESET_REG_OFFSET U(0x30)
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#define GPU_RESET_BIT (U(1) << 0)
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#define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004)
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#define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008)
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/*******************************************************************************
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* Tegra micro-seconds timer constants
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BL31_SOURCES += lib/cpus/aarch64/denver.S \
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lib/cpus/aarch64/cortex_a57.S \
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${COMMON_DIR}/drivers/gpcdma/gpcdma.c \
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${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
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${COMMON_DIR}/drivers/smmu/smmu.c \
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${SOC_DIR}/drivers/mce/mce.c \
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