allwinner: Add Allwinner A64 support
The Allwinner A64 SoC is quite popular on single board computers. It comes with four Cortex-A53 cores in a singe cluster and the usual peripherals for set-top box/tablet SoC. The ATF platform target is called "sun50i_a64". [Andre: adapted to amended directory layout, removed unneeded definitions ] Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Samuel Holland
Andre Przywara
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58032586f8
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64b3d9d88e
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Trusted Firmware-A for Allwinner ARMv8 SoCs
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===========================================
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Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Allwinner
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SoCs with ARMv8 cores. Only BL31 is used to provide proper EL3 setup and
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PSCI runtime services.
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U-Boot's SPL acts as a loader, loading both BL31 and BL33 (typically U-Boot).
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Loading is done from SD card, eMMC or SPI flash, also via an USB debug
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interface (FEL).
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BL31 lives in SRAM A2, which is documented to be accessible from secure
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world only.
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Current limitations:
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- Missing PMIC support
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After building bl31.bin, the binary must be fed to the U-Boot build system
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to include it in the FIT image that the SPL loader will process.
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bl31.bin can be either copied (or sym-linked) into U-Boot's root directory,
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or the environment variable BL31 must contain the binary's path.
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See the respective `U-Boot documentation`_ for more details.
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To build:
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::
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make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31
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.. _U-Boot documentation: http://git.denx.de/?p=u-boot.git;f=board/sunxi/README.sunxi64;hb=HEAD
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@ -64,6 +64,16 @@ Files:
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- plat/hisilicon/hikey/\*
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- plat/hisilicon/hikey960/\*
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Allwinner ARMv8 platform sub-maintainer
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---------------------------------------
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Andre Przywara (andre.przywara@arm.com, `Andre-ARM`_)
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Files:
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- docs/plat/allwinner.rst
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- plat/allwinner/\*
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HiSilicon Poplar platform sub-maintainer
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----------------------------------------
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@ -151,3 +161,4 @@ Etienne Carriere (etienne.carriere@linaro.org, `etienne-lms`_)
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.. _rockchip-linux: https://github.com/rockchip-linux
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.. _etienne-lms: https://github.com/etienne-lms
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.. _qoriq-open-source: https://github.com/qoriq-open-source
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.. _Andre-ARM: https://github.com/Andre-ARM
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SUNXI_MMAP_H__
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#define __SUNXI_MMAP_H__
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/* Memory regions */
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#define SUNXI_ROM_BASE 0x00000000
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#define SUNXI_ROM_SIZE 0x00010000
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#define SUNXI_SRAM_BASE 0x00010000
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#define SUNXI_SRAM_SIZE 0x00044000
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#define SUNXI_SRAM_A1_BASE 0x00010000
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#define SUNXI_SRAM_A1_SIZE 0x00008000
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#define SUNXI_SRAM_A2_BASE 0x00044000
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#define SUNXI_SRAM_A2_SIZE 0x00010000
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#define SUNXI_SRAM_C_BASE 0x00018000
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#define SUNXI_SRAM_C_SIZE 0x0001c000
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#define SUNXI_DEV_BASE 0x01000000
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#define SUNXI_DEV_SIZE 0x01000000
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#define SUNXI_DRAM_BASE 0x40000000
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#define SUNXI_DRAM_SIZE 0x80000000
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/* Memory-mapped devices */
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#define SUNXI_CPU_MBIST_BASE 0x01502000
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#define SUNXI_CPUCFG_BASE 0x01700000
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#define SUNXI_SYSCON_BASE 0x01c00000
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#define SUNXI_SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24)
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#define SUNXI_KEYMEM_BASE 0x01c0b000
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#define SUNXI_SMHC0_BASE 0x01c0f000
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#define SUNXI_SMHC1_BASE 0x01c10000
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#define SUNXI_SMHC2_BASE 0x01c11000
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#define SUNXI_SID_BASE 0x01c14000
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#define SUNXI_MSGBOX_BASE 0x01c17000
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#define SUNXI_SPINLOCK_BASE 0x01c18000
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#define SUNXI_CCU_BASE 0x01c20000
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#define SUNXI_PIO_BASE 0x01c20800
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#define SUNXI_TIMER_BASE 0x01c20c00
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#define SUNXI_WDOG_BASE 0x01c20ca0
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#define SUNXI_THS_BASE 0x01c25000
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#define SUNXI_UART0_BASE 0x01c28000
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#define SUNXI_UART1_BASE 0x01c28400
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#define SUNXI_UART2_BASE 0x01c28800
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#define SUNXI_UART3_BASE 0x01c28c00
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#define SUNXI_I2C0_BASE 0x01c2ac00
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#define SUNXI_I2C1_BASE 0x01c2b000
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#define SUNXI_I2C2_BASE 0x01c2b400
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#define SUNXI_DRAMCOM_BASE 0x01c62000
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#define SUNXI_DRAMCTL_BASE 0x01c63000
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#define SUNXI_DRAMPHY_BASE 0x01c65000
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#define SUNXI_SPI0_BASE 0x01c68000
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#define SUNXI_SPI1_BASE 0x01c69000
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#define SUNXI_SCU_BASE 0x01c80000
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#define SUNXI_GICD_BASE 0x01c81000
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#define SUNXI_GICC_BASE 0x01c82000
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#define SUNXI_RTC_BASE 0x01f00000
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#define SUNXI_R_TIMER_BASE 0x01f00800
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#define SUNXI_R_INTC_BASE 0x01f00c00
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#define SUNXI_R_WDOG_BASE 0x01f01000
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#define SUNXI_R_PRCM_BASE 0x01f01400
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#define SUNXI_R_TWD_BASE 0x01f01800
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#define SUNXI_R_CPUCFG_BASE 0x01f01c00
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#define SUNXI_R_CIR_BASE 0x01f02000
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#define SUNXI_R_I2C_BASE 0x01f02400
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#define SUNXI_R_UART_BASE 0x01f02800
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#define SUNXI_R_PIO_BASE 0x01f02c00
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#define SUNXI_R_RSB_BASE 0x01f03400
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#define SUNXI_R_PWM_BASE 0x01f03800
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#endif /* __SUNXI_MMAP_H__ */
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#
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# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include lib/xlat_tables_v2/xlat_tables.mk
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AW_PLAT := plat/allwinner
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PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
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-Iinclude/plat/arm/common/aarch64 \
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-I${AW_PLAT}/common/include \
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-I${AW_PLAT}/${PLAT}/include
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PLAT_BL_COMMON_SOURCES := drivers/console/${ARCH}/console.S \
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drivers/ti/uart/${ARCH}/16550_console.S \
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${XLAT_TABLES_LIB_SRCS} \
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${AW_PLAT}/common/plat_helpers.S \
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${AW_PLAT}/common/sunxi_common.c
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BL31_SOURCES += drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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lib/cpus/${ARCH}/cortex_a53.S \
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plat/common/plat_gicv2.c \
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plat/common/plat_psci_common.c \
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${AW_PLAT}/common/sunxi_bl31_setup.c \
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${AW_PLAT}/common/sunxi_pm.c \
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${AW_PLAT}/common/sunxi_topology.c
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# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
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COLD_BOOT_SINGLE_CPU := 1
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# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
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ERRATA_A53_835769 := 1
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ERRATA_A53_843419 := 1
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ERRATA_A53_855873 := 1
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# Disable the PSCI platform compatibility layer.
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ENABLE_PLAT_COMPAT := 0
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MULTI_CONSOLE_API := 1
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# Prohibit using deprecated interfaces. We rely on this for this platform.
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ERROR_DEPRECATED := 1
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# The reset vector can be changed for each CPU.
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PROGRAMMABLE_RESET_ADDRESS := 1
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# Allow mapping read-only data as execute-never.
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SEPARATE_CODE_AND_RODATA := 1
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# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
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RESET_TO_BL31 := 1
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