diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h
index 38de1b715..7bdb36def 100644
--- a/plat/st/stm32mp1/include/stm32mp1_private.h
+++ b/plat/st/stm32mp1/include/stm32mp1_private.h
@@ -21,6 +21,8 @@ void stm32mp1_syscfg_init(void);
 void stm32mp1_syscfg_enable_io_compensation_start(void);
 void stm32mp1_syscfg_enable_io_compensation_finish(void);
 void stm32mp1_syscfg_disable_io_compensation(void);
+uint32_t stm32mp1_syscfg_get_chip_version(void);
+uint32_t stm32mp1_syscfg_get_chip_dev_id(void);
 
 void stm32mp1_deconfigure_uart_pins(void);
 
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 917b8db82..738cd8cc4 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -289,6 +289,10 @@ void stm32mp1_deconfigure_uart_pins(void)
 
 uint32_t stm32mp_get_chip_version(void)
 {
+#if STM32MP13
+	return stm32mp1_syscfg_get_chip_version();
+#endif
+#if STM32MP15
 	uint32_t version = 0U;
 
 	if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) {
@@ -297,10 +301,15 @@ uint32_t stm32mp_get_chip_version(void)
 	}
 
 	return version;
+#endif
 }
 
 uint32_t stm32mp_get_chip_dev_id(void)
 {
+#if STM32MP13
+	return stm32mp1_syscfg_get_chip_dev_id();
+#endif
+#if STM32MP15
 	uint32_t dev_id;
 
 	if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) {
@@ -309,6 +318,7 @@ uint32_t stm32mp_get_chip_dev_id(void)
 	}
 
 	return dev_id;
+#endif
 }
 
 static uint32_t get_part_number(void)
diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c
index 6d24b0e85..1aabe65ba 100644
--- a/plat/st/stm32mp1/stm32mp1_syscfg.c
+++ b/plat/st/stm32mp1/stm32mp1_syscfg.c
@@ -9,6 +9,7 @@
 #include <drivers/delay_timer.h>
 #include <drivers/st/stpmic1.h>
 #include <lib/mmio.h>
+#include <lib/utils_def.h>
 
 #include <platform_def.h>
 #include <stm32mp_common.h>
@@ -26,6 +27,7 @@
 #define SYSCFG_CMPCR				0x20U
 #define SYSCFG_CMPENSETR			0x24U
 #define SYSCFG_CMPENCLRR			0x28U
+#define SYSCFG_IDC				0x380U
 
 #define CMPCR_CMPENSETR_OFFSET			0x4U
 #define CMPCR_CMPENCLRR_OFFSET			0x8U
@@ -70,6 +72,13 @@
  */
 #define SYSCFG_CMPENSETR_MPU_EN			BIT(0)
 
+/*
+ * SYSCFG_IDC Register
+ */
+#define SYSCFG_IDC_DEV_ID_MASK			GENMASK(11, 0)
+#define SYSCFG_IDC_REV_ID_MASK			GENMASK(31, 16)
+#define SYSCFG_IDC_REV_ID_SHIFT			16
+
 static void enable_io_comp_cell_finish(uintptr_t cmpcr_off)
 {
 	uint64_t start;
@@ -225,3 +234,22 @@ void stm32mp1_syscfg_disable_io_compensation(void)
 
 	clk_disable(SYSCFG);
 }
+
+/*
+ * @brief  Get silicon revision from SYSCFG registers.
+ * @retval chip version (REV_ID).
+ */
+uint32_t stm32mp1_syscfg_get_chip_version(void)
+{
+	return (mmio_read_32(SYSCFG_BASE + SYSCFG_IDC) &
+		SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT;
+}
+
+/*
+ * @brief  Get device ID from SYSCFG registers.
+ * @retval device ID (DEV_ID).
+ */
+uint32_t stm32mp1_syscfg_get_chip_dev_id(void)
+{
+	return mmio_read_32(SYSCFG_BASE + SYSCFG_IDC) & SYSCFG_IDC_DEV_ID_MASK;
+}