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xlat v2: Turn MMU parameters into 64-bit values 

Most registers are 64-bit wide, even in AArch32 mode:

- MAIR_ELx is equivalent to MAIR0 and MAIR1.
- TTBR is 64 bit in both AArch64 and AArch32.

The only difference is the TCR register, which is 32 bit in AArch32 and
in EL3 in AArch64. For consistency with the rest of ELs in AArch64, it
makes sense to also have it as a 64-bit value.

Change-Id: I2274d66a28876702e7085df5f8aad0e7ec139da9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Antonio Nino Diaz 2018-07-12 15:44:42 +01:00
parent aa1d5f6047
commit 6563c0beb8
5 changed files with 40 additions and 45 deletions
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11
include/lib/xlat_tables/xlat_tables_v2_helpers.h
View File

@ -16,12 +16,11 @@
#error "Do not include this header file directly. Include xlat_tables_v2.h instead."
#endif
/* Offsets into mmu_cfg_params array. All parameters are 32 bits wide. */
#define MMU_CFG_MAIR0 0
/* Offsets into mmu_cfg_params array. All parameters are 64 bits wide. */
#define MMU_CFG_MAIR 0
#define MMU_CFG_TCR 1
#define MMU_CFG_TTBR0_LO 2
#define MMU_CFG_TTBR0_HI 3
#define MMU_CFG_PARAM_MAX 4
#define MMU_CFG_TTBR0 2
#define MMU_CFG_PARAM_MAX 3
#ifndef __ASSEMBLY__
@ -32,7 +31,7 @@
#include <xlat_tables_defs.h>
/* Parameters of register values required when enabling MMU */
extern uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
extern uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
/* Forward declaration */
struct mmap_region;

12
lib/xlat_tables_v2/aarch32/enable_mmu.S
View File

@ -24,17 +24,17 @@ func enable_mmu_direct
mov r3, r0
ldr r0, =mmu_cfg_params
/* MAIR0 */
ldr r1, [r0, #(MMU_CFG_MAIR0 << 2)]
/* MAIR0. Only the lower 32 bits are used. */
ldr r1, [r0, #(MMU_CFG_MAIR << 3)]
stcopr r1, MAIR0
/* TTBCR */
ldr r2, [r0, #(MMU_CFG_TCR << 2)]
/* TTBCR. Only the lower 32 bits are used. */
ldr r2, [r0, #(MMU_CFG_TCR << 3)]
stcopr r2, TTBCR
/* TTBR0 */
ldr r1, [r0, #(MMU_CFG_TTBR0_LO << 2)]
ldr r2, [r0, #(MMU_CFG_TTBR0_HI << 2)]
ldr r1, [r0, #(MMU_CFG_TTBR0 << 3)]
ldr r2, [r0, #((MMU_CFG_TTBR0 << 3) + 4)]
stcopr16 r1, r2, TTBR0_64
/* TTBR1 is unused right now; set it to 0. */

24
lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
View File

@ -18,7 +18,7 @@
#error ARMv7 target does not support LPAE MMU descriptors
#endif
uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
/*
* Returns 1 if the provided granule size is supported, 0 otherwise.
@ -113,16 +113,16 @@ void setup_mmu_cfg(unsigned int flags, const uint64_t *base_table,
unsigned long long max_pa, uintptr_t max_va,
__unused int xlat_regime)
{
u_register_t mair0, ttbcr;
uint64_t ttbr0;
uint64_t mair, ttbr0;
uint32_t ttbcr;
assert(IS_IN_SECURE());
/* Set attributes in the right indices of the MAIR */
mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
mair = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
mair |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
ATTR_IWBWA_OWBWA_NTR_INDEX);
mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE,
mair |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE,
ATTR_NON_CACHEABLE_INDEX);
/*
@ -170,17 +170,17 @@ void setup_mmu_cfg(unsigned int flags, const uint64_t *base_table,
/* Set TTBR0 bits as well */
ttbr0 = (uint64_t)(uintptr_t) base_table;
#if ARM_ARCH_AT_LEAST(8, 2)
/*
* Enable CnP bit so as to share page tables with all PEs.
* Mandatory for ARMv8.2 implementations.
* Enable CnP bit so as to share page tables with all PEs. This
* is mandatory for ARMv8.2 implementations.
*/
ttbr0 |= TTBR_CNP_BIT;
#endif
/* Now populate MMU configuration */
mmu_cfg_params[MMU_CFG_MAIR0] = mair0;
mmu_cfg_params[MMU_CFG_TCR] = ttbcr;
mmu_cfg_params[MMU_CFG_TTBR0_LO] = (uint32_t) ttbr0;
mmu_cfg_params[MMU_CFG_TTBR0_HI] = ttbr0 >> 32;
mmu_cfg_params[MMU_CFG_MAIR] = mair;
mmu_cfg_params[MMU_CFG_TCR] = (uint64_t) ttbcr;
mmu_cfg_params[MMU_CFG_TTBR0] = ttbr0;
}

8
lib/xlat_tables_v2/aarch64/enable_mmu.S
View File

@ -43,17 +43,15 @@
ldr x0, =mmu_cfg_params
/* MAIR */
ldr w1, [x0, #(MMU_CFG_MAIR0 << 2)]
ldr x1, [x0, #(MMU_CFG_MAIR << 3)]
_msr mair, \el, x1
/* TCR */
ldr w2, [x0, #(MMU_CFG_TCR << 2)]
ldr x2, [x0, #(MMU_CFG_TCR << 3)]
_msr tcr, \el, x2
/* TTBR */
ldr w3, [x0, #(MMU_CFG_TTBR0_LO << 2)]
ldr w4, [x0, #(MMU_CFG_TTBR0_HI << 2)]
orr x3, x3, x4, lsl #32
ldr x3, [x0, #(MMU_CFG_TTBR0 << 3)]
_msr ttbr0, \el, x3
/*

30
lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
View File

@ -13,7 +13,7 @@
#include <xlat_tables_v2.h>
#include "../xlat_tables_private.h"
uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
/*
* Returns 1 if the provided granule size is supported, 0 otherwise.
@ -183,7 +183,7 @@ int xlat_arch_current_el(void)
void setup_mmu_cfg(unsigned int flags, const uint64_t *base_table,
unsigned long long max_pa, uintptr_t max_va, int xlat_regime)
{
uint64_t mair, ttbr, tcr;
uint64_t mair, ttbr0, tcr;
uintptr_t virtual_addr_space_size;
/* Set attributes in the right indices of the MAIR. */
@ -191,8 +191,6 @@ void setup_mmu_cfg(unsigned int flags, const uint64_t *base_table,
mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX);
mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX);
ttbr = (uint64_t) base_table;
/*
* Limit the input address ranges and memory region sizes translated
* using TTBR0 to the given virtual address space size.
@ -239,18 +237,18 @@ void setup_mmu_cfg(unsigned int flags, const uint64_t *base_table,
tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT);
}
mmu_cfg_params[MMU_CFG_MAIR0] = (uint32_t) mair;
mmu_cfg_params[MMU_CFG_TCR] = (uint32_t) tcr;
/* Set TTBR bits as well */
if (ARM_ARCH_AT_LEAST(8, 2)) {
/*
* Enable CnP bit so as to share page tables with all PEs. This
* is mandatory for ARMv8.2 implementations.
*/
ttbr |= TTBR_CNP_BIT;
}
ttbr0 = (uint64_t) base_table;
mmu_cfg_params[MMU_CFG_TTBR0_LO] = (uint32_t) ttbr;
mmu_cfg_params[MMU_CFG_TTBR0_HI] = (uint32_t) (ttbr >> 32);
#if ARM_ARCH_AT_LEAST(8, 2)
/*
* Enable CnP bit so as to share page tables with all PEs. This
* is mandatory for ARMv8.2 implementations.
*/
ttbr0 |= TTBR_CNP_BIT;
#endif
mmu_cfg_params[MMU_CFG_MAIR] = mair;
mmu_cfg_params[MMU_CFG_TCR] = tcr;
mmu_cfg_params[MMU_CFG_TTBR0] = ttbr0;
}