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mediatek: mt8183: switch PLL/CLKSQ/ck_off/axi_26m control to SPM 

1. Switch ARMPLL_LL/CCIPLL/MAINPLL/MPLL control to SPM
2. Switch CLKSQ1/TDCLKSQ control to SPM
3. Switch ck_off/axi_26m control to SPM

BUG=b:136980838
TEST=system suspend/resume passed

Change-Id: I5c8506f7cf16d5cdaeb5ef8caa60a2992a361e18
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
This commit is contained in:
Roger Lu 2019-10-28 21:11:48 +08:00 committed by kenny liang
parent 1d2b41614c
commit 658cb0725f
2 changed files with 31 additions and 0 deletions
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24
plat/mediatek/mt8183/drivers/spm/spm.c
View File

@ -12,6 +12,21 @@
DEFINE_BAKERY_LOCK(spm_lock);
/* CLK_SCP_CFG_0 */
#define SPM_CK_OFF_CONTROL (0x3FF)
/* CLK_SCP_CFG_1 */
#define SPM_AXI_26M_SEL (0x1)
/* AP_PLL_CON3 */
#define SPM_PLL_CONTROL (0x7FAAAAF)
/* AP_PLL_CON4 */
#define SPM_PLL_OUT_OFF_CONTROL (0xFA0A)
/* AP_PLL_CON6 */
#define PLL_DLY (0x20000)
const char *wakeup_src_str[32] = {
[0] = "R12_PCM_TIMER",
[1] = "R12_SSPM_WDT_EVENT_B",
@ -324,5 +339,14 @@ void spm_boot_init(void)
spm_lock_init();
mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
/* switch ck_off/axi_26m control to SPM */
mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL);
mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL);
/* switch PLL/CLKSQ control to SPM */
mmio_clrbits_32(AP_PLL_CON3, SPM_PLL_CONTROL);
mmio_clrbits_32(AP_PLL_CON4, SPM_PLL_OUT_OFF_CONTROL);
mmio_clrbits_32(AP_PLL_CON6, PLL_DLY);
NOTICE("%s() end\n", __func__);
}

7
plat/mediatek/mt8183/include/platform_def.h
View File

@ -39,7 +39,14 @@
#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
#define TOPCKGEN_BASE (IO_PHYS + 0x0)
#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200)
#define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x204)
#define APMIXEDSYS (IO_PHYS + 0xC000)
#define AP_PLL_CON3 (APMIXEDSYS + 0xC)
#define AP_PLL_CON4 (APMIXEDSYS + 0x10)
#define AP_PLL_CON6 (APMIXEDSYS + 0x18)
#define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200)
#define ARMPLL_L_CON0 (APMIXEDSYS + 0x210)
#define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c)