mediatek: mt8183: switch PLL/CLKSQ/ck_off/axi_26m control to SPM
1. Switch ARMPLL_LL/CCIPLL/MAINPLL/MPLL control to SPM 2. Switch CLKSQ1/TDCLKSQ control to SPM 3. Switch ck_off/axi_26m control to SPM BUG=b:136980838 TEST=system suspend/resume passed Change-Id: I5c8506f7cf16d5cdaeb5ef8caa60a2992a361e18 Signed-off-by: Roger Lu <roger.lu@mediatek.com>
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@ -12,6 +12,21 @@
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DEFINE_BAKERY_LOCK(spm_lock);
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DEFINE_BAKERY_LOCK(spm_lock);
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/* CLK_SCP_CFG_0 */
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#define SPM_CK_OFF_CONTROL (0x3FF)
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/* CLK_SCP_CFG_1 */
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#define SPM_AXI_26M_SEL (0x1)
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/* AP_PLL_CON3 */
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#define SPM_PLL_CONTROL (0x7FAAAAF)
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/* AP_PLL_CON4 */
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#define SPM_PLL_OUT_OFF_CONTROL (0xFA0A)
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/* AP_PLL_CON6 */
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#define PLL_DLY (0x20000)
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const char *wakeup_src_str[32] = {
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const char *wakeup_src_str[32] = {
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[0] = "R12_PCM_TIMER",
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[0] = "R12_PCM_TIMER",
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[1] = "R12_SSPM_WDT_EVENT_B",
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[1] = "R12_SSPM_WDT_EVENT_B",
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@ -324,5 +339,14 @@ void spm_boot_init(void)
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spm_lock_init();
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spm_lock_init();
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mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
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mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
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/* switch ck_off/axi_26m control to SPM */
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mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL);
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mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL);
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/* switch PLL/CLKSQ control to SPM */
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mmio_clrbits_32(AP_PLL_CON3, SPM_PLL_CONTROL);
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mmio_clrbits_32(AP_PLL_CON4, SPM_PLL_OUT_OFF_CONTROL);
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mmio_clrbits_32(AP_PLL_CON6, PLL_DLY);
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NOTICE("%s() end\n", __func__);
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NOTICE("%s() end\n", __func__);
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}
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}
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@ -39,7 +39,14 @@
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#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
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#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
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#define TOPCKGEN_BASE (IO_PHYS + 0x0)
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#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200)
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#define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x204)
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#define APMIXEDSYS (IO_PHYS + 0xC000)
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#define APMIXEDSYS (IO_PHYS + 0xC000)
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#define AP_PLL_CON3 (APMIXEDSYS + 0xC)
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#define AP_PLL_CON4 (APMIXEDSYS + 0x10)
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#define AP_PLL_CON6 (APMIXEDSYS + 0x18)
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#define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200)
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#define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200)
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#define ARMPLL_L_CON0 (APMIXEDSYS + 0x210)
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#define ARMPLL_L_CON0 (APMIXEDSYS + 0x210)
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#define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c)
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#define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c)
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