From 67bc721b2bc321e07b1ea50c53dd35915dc2a949 Mon Sep 17 00:00:00 2001
From: Varun Wadekar <vwadekar@nvidia.com>
Date: Wed, 17 Feb 2016 10:10:50 -0800
Subject: [PATCH] Tegra: memctrl_v2: check GPU state before VPR programming

The GPU is the real consumer of the video protected memory region
and it needs to be in reset to pick up the new region.

This patch checks if the GPU is in reset before we program the new
video protected memory region settings.

Change-Id: I44f553bfcf07b1975abad53b245954be966c8aeb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
---
 .../tegra/common/drivers/memctrl/memctrl_v2.c    | 16 ++++++++++++++++
 plat/nvidia/tegra/soc/t186/plat_setup.c          |  2 ++
 plat/nvidia/tegra/soc/t186/platform_t186.mk      |  4 ++--
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index 97ae3b261..27c878971 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -39,6 +39,9 @@
 #include <tegra_def.h>
 #include <xlat_tables.h>
 
+#define TEGRA_GPU_RESET_REG_OFFSET	0x30
+#define  GPU_RESET_BIT			(1 << 0)
+
 /* Video Memory base and size (live values) */
 static uint64_t video_mem_base;
 static uint64_t video_mem_size;
@@ -334,6 +337,19 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
  */
 void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
 {
+	uint32_t regval;
+
+	/*
+	 * The GPU is the user of the Video Memory region. In order to
+	 * transition to the new memory region smoothly, we program the
+	 * new base/size ONLY if the GPU is in reset mode.
+	 */
+	regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET);
+	if ((regval & GPU_RESET_BIT) == 0) {
+		ERROR("GPU not in reset! Video Memory setup failed\n");
+		return;
+	}
+
 	/*
 	 * Setup the Memory controller to restrict CPU accesses to the Video
 	 * Memory region
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index 626035119..0496f5a5e 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -63,6 +63,8 @@ static const mmap_region_t tegra_mmap[] = {
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
 			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */
+			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk
index 5e55d9d0c..777f2db21 100644
--- a/plat/nvidia/tegra/soc/t186/platform_t186.mk
+++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk
@@ -42,10 +42,10 @@ $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
 PLATFORM_MAX_CPUS_PER_CLUSTER		:= 4
 $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
 
-MAX_XLAT_TABLES				:= 10
+MAX_XLAT_TABLES				:= 12
 $(eval $(call add_define,MAX_XLAT_TABLES))
 
-MAX_MMAP_REGIONS			:= 10
+MAX_MMAP_REGIONS			:= 12
 $(eval $(call add_define,MAX_MMAP_REGIONS))
 
 # platform files