feat(mpmm): add support for MPMM
MPMM - the Maximum Power Mitigation Mechanism - is an optional microarchitectural feature present on some Armv9-A cores, introduced with the Cortex-X2, Cortex-A710 and Cortex-A510 cores. MPMM allows the SoC firmware to detect and limit high activity events to assist in SoC processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. This feature is enabled via the `ENABLE_MPMM` build option. Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or by via the plaform-implemented `plat_mpmm_topology` function. Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167 Signed-off-by: Chris Kay <chris.kay@arm.com>
This commit is contained in:
Chris Kay
parent
742ca2307f
commit
68120783d6
4
Makefile
4
Makefile
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@ -1015,6 +1015,8 @@ $(eval $(call assert_booleans,\
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ENABLE_SYS_REG_TRACE_FOR_NS \
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ENABLE_TRF_FOR_NS \
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ENABLE_FEAT_HCX \
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ENABLE_MPMM \
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ENABLE_MPMM_FCONF \
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)))
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$(eval $(call assert_numerics,\
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@ -1123,6 +1125,8 @@ $(eval $(call add_defines,\
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ENABLE_SYS_REG_TRACE_FOR_NS \
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ENABLE_TRF_FOR_NS \
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ENABLE_FEAT_HCX \
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ENABLE_MPMM \
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ENABLE_MPMM_FCONF \
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)))
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ifeq (${SANITIZE_UB},trap)
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@ -23,6 +23,7 @@ ifeq (${SPM_MM},1)
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endif
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include lib/extensions/amu/amu.mk
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include lib/mpmm/mpmm.mk
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include lib/psci/psci_lib.mk
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BL31_SOURCES += bl31/bl31_main.c \
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@ -82,6 +83,10 @@ ifeq (${ENABLE_AMU},1)
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BL31_SOURCES += ${AMU_SOURCES}
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endif
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ifeq (${ENABLE_MPMM},1)
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BL31_SOURCES += ${MPMM_SOURCES}
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endif
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ifeq (${ENABLE_SVE_FOR_NS},1)
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BL31_SOURCES += lib/extensions/sve/sve.c
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endif
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@ -10,6 +10,8 @@ When the ``ENABLE_AMU=1`` build option is provided, Trusted Firmware-A sets up
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the |AMU| prior to its exit from EL3, and will save and restore architected
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|AMU| counters as necessary upon suspend and resume.
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.. _Activity Monitor Auxiliary Counters:
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Auxiliary counters
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------------------
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@ -146,3 +146,4 @@ Properties binding information
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fconf_properties
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amu-bindings
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mpmm-bindings
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@ -0,0 +1,48 @@
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Maximum Power Mitigation Mechanism (MPMM) Bindings
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==================================================
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|MPMM| support cannot be determined at runtime by the firmware. Instead, these
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DTB bindings allow the platform to communicate per-core support for |MPMM| via
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the ``HW_CONFIG`` device tree blob.
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Bindings
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^^^^^^^^
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.. contents::
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:local:
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``/cpus/cpus/cpu*`` node properties
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"""""""""""""""""""""""""""""""""""
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The ``cpu`` node has been augmented to allow the platform to indicate support
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for |MPMM| on a given core.
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+-------------------+-------+-------------+------------------------------------+
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| Property name | Usage | Value type | Description |
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+===================+=======+=============+====================================+
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| ``supports-mpmm`` | O | ``<empty>`` | If present, indicates that |MPMM| |
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| | | | is available on this core. |
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+-------------------+-------+-------------+------------------------------------+
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Example
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^^^^^^^
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An example system offering two cores, one with support for |MPMM| and one
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without, can be described as follows:
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.. code-block::
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0@00000 {
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...
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supports-mpmm;
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};
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cpu1@00100 {
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...
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};
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}
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@ -14,6 +14,7 @@ Components
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fconf/index
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firmware-update
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measured_boot/index
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mpmm
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platform-interrupt-controller-API
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ras
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romlib-design
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@ -0,0 +1,30 @@
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Maximum Power Mitigation Mechanism (MPMM)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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|MPMM| is an optional microarchitectural power management mechanism supported by
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some Arm Armv9-A cores, beginning with the Cortex-X2, Cortex-A710 and
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Cortex-A510 cores. This mechanism detects and limits high-activity events to
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assist in |SoC| processor power domain dynamic power budgeting and limit the
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triggering of whole-rail (i.e. clock chopping) responses to overcurrent
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conditions.
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|MPMM| is enabled on a per-core basis by the EL3 runtime firmware. The presence
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of |MPMM| cannot be determined at runtime by the firmware, and therefore the
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platform must expose this information through one of two possible mechanisms:
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- |FCONF|, controlled by the ``ENABLE_MPMM_FCONF`` build option.
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- A platform implementation of the ``plat_mpmm_topology`` function (the
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default).
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See :ref:`Maximum Power Mitigation Mechanism (MPMM) Bindings` for documentation
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on the |FCONF| device tree bindings.
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.. warning::
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|MPMM| exposes gear metrics through the auxiliary |AMU| counters. An
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external power controller can use these metrics to budget SoC power by
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limiting the number of cores that can execute higher-activity workloads or
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switching to a different DVFS operating point. When this is the case, the
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|AMU| counters that make up the |MPMM| gears must be enabled by the EL3
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runtime firmware - please see :ref:`Activity Monitor Auxiliary Counters` for
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documentation on enabling auxiliary |AMU| counters.
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@ -265,6 +265,16 @@ Common build options
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partitioning in EL3, however. Platform initialisation code should configure
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and use partitions in EL3 as required. This option defaults to ``0``.
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- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power
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Mitigation Mechanism supported by certain Arm cores, which allows the SoC
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firmware to detect and limit high activity events to assist in SoC processor
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power domain dynamic power budgeting and limit the triggering of whole-rail
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(i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``.
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- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which
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allows platforms with cores supporting MPMM to describe them via the
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``HW_CONFIG`` device tree blob. Default is 0.
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- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
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support within generic code in TF-A. This option is currently only supported
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in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32
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@ -25,6 +25,7 @@
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.. |Linaro| replace:: :term:`Linaro`
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.. |MMU| replace:: :term:`MMU`
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.. |MPAM| replace:: :term:`MPAM`
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.. |MPMM| replace:: :term:`MPMM`
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.. |MPIDR| replace:: :term:`MPIDR`
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.. |MTE| replace:: :term:`MTE`
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.. |OEN| replace:: :term:`OEN`
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@ -92,6 +92,10 @@ You can find additional definitions in the `Arm Glossary`_.
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MPAM
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Memory Partitioning And Monitoring. An optional Armv8.4 extension.
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MPMM
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Maximum Power Mitigation Mechanism, an optional power management mechanism
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supported by some Arm Armv9-A cores.
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MPIDR
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Multiprocessor Affinity Register
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@ -1216,4 +1216,16 @@
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#define DSU_CLUSTER_PWR_ON 1
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#define DSU_CLUSTER_PWR_MASK U(1)
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/*******************************************************************************
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* Definitions for CPU Power/Performance Management registers
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******************************************************************************/
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#define CPUPPMCR_EL3 S3_6_C15_C2_0
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#define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0)
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#define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1)
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#define CPUMPMMCR_EL3 S3_6_C15_C2_1
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#define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0)
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#define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1)
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#endif /* ARCH_H */
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@ -542,6 +542,10 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
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/* DynamIQ Shared Unit power management */
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DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
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/* CPU Power/Performance Management registers */
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DEFINE_RENAME_SYSREG_RW_FUNCS(cpuppmcr_el3, CPUPPMCR_EL3)
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DEFINE_RENAME_SYSREG_RW_FUNCS(cpumpmmcr_el3, CPUMPMMCR_EL3)
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/* Armv9.2 RME Registers */
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DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3)
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DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3)
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@ -0,0 +1,20 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FCONF_MPMM_GETTER_H
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#define FCONF_MPMM_GETTER_H
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#include <lib/mpmm/mpmm.h>
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#define mpmm__config_getter(id) fconf_mpmm_config.id
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struct fconf_mpmm_config {
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const struct mpmm_topology *topology;
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};
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extern struct fconf_mpmm_config fconf_mpmm_config;
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#endif /* FCONF_MPMM_GETTER_H */
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@ -0,0 +1,57 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MPMM_H
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#define MPMM_H
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#include <stdbool.h>
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#include <platform_def.h>
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/*
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* Enable the Maximum Power Mitigation Mechanism.
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*
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* This function will enable MPMM for the current core. The AMU counters
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* representing the MPMM gears must have been configured and enabled prior to
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* calling this function.
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*/
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void mpmm_enable(void);
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/*
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* MPMM core data.
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*
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* This structure represents per-core data retrieved from the hardware
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* configuration device tree.
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*/
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struct mpmm_core {
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/*
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* Whether MPMM is supported.
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*
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* Cores with support for MPMM offer one or more auxiliary AMU counters
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* representing MPMM gears.
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*/
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bool supported;
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};
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/*
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* MPMM topology.
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*
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* This topology structure describes the system-wide representation of the
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* information retrieved from the hardware configuration device tree.
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*/
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struct mpmm_topology {
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struct mpmm_core cores[PLATFORM_CORE_COUNT]; /* Per-core data */
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};
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#if !ENABLE_MPMM_FCONF
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/*
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* Retrieve the platform's MPMM topology. A `NULL` return value is treated as a
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* non-fatal error, in which case MPMM will not be enabled for any core.
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*/
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const struct mpmm_topology *plat_mpmm_topology(void);
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#endif /* ENABLE_MPMM_FCONF */
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#endif /* MPMM_H */
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@ -23,6 +23,10 @@
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# include <lib/fconf/fconf_amu_getter.h>
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#endif
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#if ENABLE_MPMM
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# include <lib/mpmm/mpmm.h>
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#endif
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struct amu_ctx {
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uint64_t group0_cnts[AMU_GROUP0_MAX_COUNTERS];
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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@ -273,26 +277,31 @@ void amu_enable(bool el2_unused, cpu_context_t *ctx)
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/* Initialize FEAT_AMUv1p1 features if present. */
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if (id_aa64pfr0_el1_amu >= ID_AA64PFR0_AMU_V1P1) {
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return;
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}
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if (el2_unused) {
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/* Make sure virtual offsets are disabled if EL2 not used. */
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write_hcr_el2_amvoffen(0U);
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}
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if (el2_unused) {
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/*
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* Make sure virtual offsets are disabled if EL2 not
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* used.
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*/
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write_hcr_el2_amvoffen(0U);
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}
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#if AMU_RESTRICT_COUNTERS
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/*
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* FEAT_AMUv1p1 adds a register field to restrict access to group 1
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* counters at all but the highest implemented EL. This is controlled
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* with the AMU_RESTRICT_COUNTERS compile time flag, when set, system
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* register reads at lower ELs return zero. Reads from the memory
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* mapped view are unaffected.
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*/
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VERBOSE("AMU group 1 counter access restricted.\n");
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write_amcr_el0_cg1rz(1U);
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/*
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* FEAT_AMUv1p1 adds a register field to restrict access to
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* group 1 counters at all but the highest implemented EL. This
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* is controlled with the `AMU_RESTRICT_COUNTERS` compile time
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* flag, when set, system register reads at lower ELs return
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* zero. Reads from the memory mapped view are unaffected.
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*/
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VERBOSE("AMU group 1 counter access restricted.\n");
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write_amcr_el0_cg1rz(1U);
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#else
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write_amcr_el0_cg1rz(0U);
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write_amcr_el0_cg1rz(0U);
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#endif
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}
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#if ENABLE_MPMM
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mpmm_enable();
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#endif
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}
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@ -616,6 +625,10 @@ static void *amu_context_restore(const void *arg)
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}
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#endif
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#if ENABLE_MPMM
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mpmm_enable();
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#endif
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return (void *)0;
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}
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@ -14,3 +14,6 @@ FCONF_DYN_SOURCES += ${FDT_WRAPPERS_SOURCES}
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FCONF_AMU_SOURCES := lib/fconf/fconf_amu_getter.c
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FCONF_AMU_SOURCES += ${FDT_WRAPPERS_SOURCES}
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FCONF_MPMM_SOURCES := lib/fconf/fconf_mpmm_getter.c
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FCONF_MPMM_SOURCES += ${FDT_WRAPPERS_SOURCES}
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@ -0,0 +1,80 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include <common/debug.h>
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#include <common/fdt_wrappers.h>
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#include <lib/fconf/fconf.h>
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#include <lib/fconf/fconf_mpmm_getter.h>
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#include <libfdt.h>
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#include <plat/common/platform.h>
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struct fconf_mpmm_config fconf_mpmm_config;
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static struct mpmm_topology fconf_mpmm_topology;
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/*
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* Within a `cpu` node, determine support for MPMM via the `supports-mpmm`
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* property.
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*
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* Returns `0` on success, or a negative integer representing an error code.
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*/
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static int fconf_populate_mpmm_cpu(const void *fdt, int off, uintptr_t mpidr)
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{
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int ret, len;
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int core_pos;
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struct mpmm_core *core;
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core_pos = plat_core_pos_by_mpidr(mpidr);
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if (core_pos < 0) {
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return -FDT_ERR_BADVALUE;
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}
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core = &fconf_mpmm_topology.cores[core_pos];
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fdt_getprop(fdt, off, "supports-mpmm", &len);
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if (len >= 0) {
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core->supported = true;
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ret = 0;
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} else {
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core->supported = false;
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ret = len;
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}
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return ret;
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}
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/*
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* Populates the global `fconf_mpmm_config` structure based on what's described
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* by the hardware configuration device tree blob.
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*
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* The device tree is expected to provide a `supports-mpmm` property for each
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* `cpu` node, like so:
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*
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* cpu@0 {
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* supports-mpmm;
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* };
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*
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* This property indicates whether the core implements MPMM, as we cannot detect
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* support for it dynamically.
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*/
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static int fconf_populate_mpmm(uintptr_t config)
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{
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int ret = fdtw_for_each_cpu(
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(const void *)config, fconf_populate_mpmm_cpu);
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if (ret == 0) {
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fconf_mpmm_config.topology = &fconf_mpmm_topology;
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} else {
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ERROR("FCONF: failed to configure MPMM: %d\n", ret);
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}
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return ret;
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}
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FCONF_REGISTER_POPULATOR(HW_CONFIG, mpmm, fconf_populate_mpmm);
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@ -0,0 +1,72 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <lib/mpmm/mpmm.h>
|
||||
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#if ENABLE_MPMM_FCONF
|
||||
# include <lib/fconf/fconf.h>
|
||||
# include <lib/fconf/fconf_mpmm_getter.h>
|
||||
#endif
|
||||
|
||||
static uint64_t read_cpuppmcr_el3_mpmmpinctl(void)
|
||||
{
|
||||
return (read_cpuppmcr_el3() >> CPUPPMCR_EL3_MPMMPINCTL_SHIFT) &
|
||||
CPUPPMCR_EL3_MPMMPINCTL_MASK;
|
||||
}
|
||||
|
||||
static void write_cpumpmmcr_el3_mpmm_en(uint64_t mpmm_en)
|
||||
{
|
||||
uint64_t value = read_cpumpmmcr_el3();
|
||||
|
||||
value &= ~(CPUMPMMCR_EL3_MPMM_EN_MASK << CPUMPMMCR_EL3_MPMM_EN_SHIFT);
|
||||
value |= (mpmm_en & CPUMPMMCR_EL3_MPMM_EN_MASK) <<
|
||||
CPUMPMMCR_EL3_MPMM_EN_SHIFT;
|
||||
|
||||
write_cpumpmmcr_el3(value);
|
||||
}
|
||||
|
||||
static bool mpmm_supported(void)
|
||||
{
|
||||
bool supported = false;
|
||||
const struct mpmm_topology *topology;
|
||||
|
||||
#if ENABLE_MPMM_FCONF
|
||||
topology = FCONF_GET_PROPERTY(mpmm, config, topology);
|
||||
#else
|
||||
topology = plat_mpmm_topology();
|
||||
#endif /* ENABLE_MPMM_FCONF */
|
||||
|
||||
/*
|
||||
* For the current core firstly try to find out if the platform
|
||||
* configuration has claimed support for MPMM, then make sure that MPMM
|
||||
* is controllable through the system registers.
|
||||
*/
|
||||
|
||||
if (topology != NULL) {
|
||||
unsigned int core_pos = plat_my_core_pos();
|
||||
|
||||
supported = topology->cores[core_pos].supported &&
|
||||
(read_cpuppmcr_el3_mpmmpinctl() == 0U);
|
||||
} else {
|
||||
ERROR("MPMM: failed to generate MPMM topology\n");
|
||||
}
|
||||
|
||||
return supported;
|
||||
}
|
||||
|
||||
void mpmm_enable(void)
|
||||
{
|
||||
bool supported = mpmm_supported();
|
||||
|
||||
if (supported) {
|
||||
write_cpumpmmcr_el3_mpmm_en(1U);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
#
|
||||
# Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
include lib/extensions/amu/amu.mk
|
||||
include lib/fconf/fconf.mk
|
||||
|
||||
ifneq (${ENABLE_MPMM},0)
|
||||
ifneq ($(ARCH),aarch64)
|
||||
$(error MPMM support (`ENABLE_MPMM`) can only be enabled in AArch64 images (`ARCH`))
|
||||
endif
|
||||
|
||||
ifeq (${ENABLE_AMU_AUXILIARY_COUNTERS},0) # For MPMM gear AMU counters
|
||||
$(error MPMM support (`ENABLE_MPM`) requires auxiliary AMU counter support (`ENABLE_AMU_AUXILIARY_COUNTERS`))
|
||||
endif
|
||||
endif
|
||||
|
||||
MPMM_SOURCES := lib/mpmm/mpmm.c
|
||||
MPMM_SOURCES += ${AMU_SOURCES}
|
||||
|
||||
ifneq (${ENABLE_MPMM_FCONF},0)
|
||||
ifeq (${ENABLE_MPMM},0)
|
||||
$(error MPMM FCONF support (`ENABLE_MPMM_FCONF`) requires MPMM support (`ENABLE_MPMM`))
|
||||
endif
|
||||
|
||||
MPMM_SOURCES += ${FCONF_MPMM_SOURCES}
|
||||
endif
|
||||
|
|
@ -96,6 +96,12 @@ DYN_DISABLE_AUTH := 0
|
|||
# Build option to enable MPAM for lower ELs
|
||||
ENABLE_MPAM_FOR_LOWER_ELS := 0
|
||||
|
||||
# Enable the Maximum Power Mitigation Mechanism on supporting cores.
|
||||
ENABLE_MPMM := 0
|
||||
|
||||
# Enable MPMM configuration via FCONF.
|
||||
ENABLE_MPMM_FCONF := 0
|
||||
|
||||
# Flag to Enable Position Independant support (PIE)
|
||||
ENABLE_PIE := 0
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue