docs: Update user guide
Make sure the steps in the user guide are up to date and can be performed out of the box. Change-Id: Ib4d959aa771cf515f74e150aaee2fbad24c18c38 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent
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@ -413,7 +413,7 @@ Common build options
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and use partitions in EL3 as required. This option defaults to ``0``.
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- ``ENABLE_PAUTH``: Boolean option to enable ARMv8.3 Pointer Authentication
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support for TF-A BL images itself. If enabled, it is needed to use a compiler
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support for TF-A BL images itself. If enabled, it is needed to use a compiler
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that supports the option ``-msign-return-address``. This flag defaults to 0
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and this is an experimental feature.
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Note that Pointer Authentication is enabled for Non-secure world irrespective
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@ -1014,18 +1014,13 @@ For AArch64:
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::
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make PLAT=fvp BL33=<path/to/bl33.bin> fip
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make PLAT=fvp BL33=<path-to>/bl33.bin fip
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For AArch32:
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::
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make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip
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Note that AArch32 support for Normal world boot loader (BL33), like U-boot or
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UEFI, on FVP is not available upstream. Hence custom solutions are required to
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allow Linux boot on FVP. These instructions assume such a custom boot loader
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(BL33) is available.
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make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path-to>/bl33.bin fip
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The resulting FIP may be found in:
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@ -1276,8 +1271,7 @@ section for more info on selecting the right FDT to use.
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make [DEBUG=1] [V=1] fiptool
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# Unpack firmware images from Linaro FIP
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./tools/fiptool/fiptool unpack \
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<path/to/linaro/release>/fip.bin
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./tools/fiptool/fiptool unpack <path-to-linaro-release>/fip.bin
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The unpack operation will result in a set of binary images extracted to the
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current working directory. The SCP_BL2 image corresponds to
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@ -1287,8 +1281,8 @@ section for more info on selecting the right FDT to use.
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exist in the current directory. If that is the case, either delete those
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files or use the ``--force`` option to overwrite.
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Note: For AArch32, the instructions below assume that nt-fw.bin is a custom
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Normal world boot loader that supports AArch32.
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Note: For AArch32, the instructions below assume that nt-fw.bin is a normal
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world boot loader that supports AArch32.
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#. Build TF-A images and create a new FIP for FVP
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@ -1309,9 +1303,7 @@ section for more info on selecting the right FDT to use.
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::
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make PLAT=juno all fip \
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BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \
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SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin
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make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip
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For AArch32:
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@ -1333,6 +1325,13 @@ section for more info on selecting the right FDT to use.
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make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
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RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
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- Save ``bl32.bin`` to a temporary location and clean the build products.
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::
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cp <path-to-build>/bl32.bin <path-to-temporary>
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make realclean
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- Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
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must point to the AArch64 Linaro cross compiler.
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@ -1346,9 +1345,8 @@ section for more info on selecting the right FDT to use.
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::
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make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
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BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \
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SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin \
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BL32=<path-to-bl32>/bl32.bin all fip
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BL33=nt-fw.bin SCP_BL2=scp-fw.bin \
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BL32=<path-to-temporary>/bl32.bin all fip
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The resulting BL1 and FIP images may be found in:
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@ -1504,7 +1502,7 @@ used:
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::
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-C bp.flashloader1.fname="/path/to/el3-payload"
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-C bp.flashloader1.fname="<path-to>/<el3-payload>"
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On Foundation FVP, there is no flash loader component and the EL3 payload
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may be programmed anywhere in flash using method 3 below.
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@ -1514,15 +1512,15 @@ used:
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::
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load /path/to/el3-payload.elf
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load <path-to>/el3-payload.elf
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#. The EL3 payload may be pre-loaded in volatile memory using the following
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model parameters:
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::
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--data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs]
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--data="/path/to/el3-payload"@address [Foundation FVP]
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--data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
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--data="<path-to>/<el3-payload>"@address [Foundation FVP]
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The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
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used when building TF-A.
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@ -1650,12 +1648,10 @@ The latest version of the AArch64 build of TF-A has been tested on the following
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Arm FVPs without shifted affinities, and that do not support threaded CPU cores
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(64-bit host machine only).
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NOTE: Unless otherwise stated, the model version is Version 11.4 Build 37.
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The FVP models used are Version 11.5 Build 33, unless otherwise stated.
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- ``FVP_Base_Aresx4``
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- ``FVP_Base_AEMv8A-AEMv8A``
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- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
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- ``FVP_Base_AEMv8A-AEMv8A``
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- ``FVP_Base_RevC-2xAEMv8A``
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- ``FVP_Base_Cortex-A32x4``
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- ``FVP_Base_Cortex-A35x4``
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@ -1670,7 +1666,8 @@ NOTE: Unless otherwise stated, the model version is Version 11.4 Build 37.
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- ``FVP_Base_Cortex-A73x4``
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- ``FVP_Base_Cortex-A75x4``
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- ``FVP_Base_Cortex-A76x4``
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- ``FVP_CSS_SGI-575`` (Version 11.3 build 40)
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- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
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- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
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- ``Foundation_Platform``
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The latest version of the AArch32 build of TF-A has been tested on the following
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@ -1832,6 +1829,9 @@ with 8 CPUs using the AArch64 build of TF-A.
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
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Note: The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
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specific DTS for all the CPUs to be loaded.
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Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -1928,7 +1928,7 @@ with 8 CPUs using the AArch64 build of TF-A.
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Notes:
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- Since Position Independent Executable (PIE) support is enabled for BL31
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- If Position Independent Executable (PIE) support is enabled for BL31
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in this config, it can be loaded at any valid address for execution.
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- Since a FIP is not loaded when using BL31 as reset entrypoint, the
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@ -1939,6 +1939,9 @@ Notes:
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and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
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parameter.
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- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
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specific DTS for all the CPUs to be loaded.
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- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
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X and Y are the cluster and CPU numbers respectively, is used to set the
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reset vector for each core.
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@ -2107,4 +2110,4 @@ wakeup interrupt from RTC.
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.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
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.. _Secure Partition Manager Design guide: secure-partition-manager-design.rst
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.. _`Trusted Firmware-A Coding Guidelines`: coding-guidelines.rst
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_`Library at ROM`: romlib-design.rst
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_`Library at ROM`: romlib-design.rst
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