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Rework memory information passing to BL3-x images 

The issues addressed in this patch are:

1. Remove meminfo_t from the common interfaces in BL3-x,
expecting that platform code will find a suitable mechanism
to determine the memory extents in these images and provide
it to the BL3-x images.

2. Remove meminfo_t and bl31_plat_params_t from all FVP BL3-x
code as the images use link-time information to determine
memory extents.

meminfo_t is still used by common interface in BL1/BL2 for
loading images

Change-Id: I4e825ebf6f515b59d84dc2bdddf6edbf15e2d60f
This commit is contained in:
Vikram Kanigiri 2014-05-16 18:48:12 +01:00
parent 4112bfa0c2
commit 6871c5d3a2
15 changed files with 102 additions and 215 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
bl2/bl2_main.c
View File

@ -67,9 +67,10 @@ void bl2_main(void)
{
meminfo_t *bl2_tzram_layout;
bl31_params_t *bl2_to_bl31_params;
bl31_plat_params_t *bl2_to_bl31_plat_params;
unsigned int bl2_load, bl31_load;
entry_point_info_t *bl31_ep_info;
meminfo_t bl32_mem_info;
meminfo_t bl33_mem_info;
int e;
/* Perform remaining generic architectural setup in S-El1 */
@ -88,7 +89,6 @@ void bl2_main(void)
* information to BL31.
*/
bl2_to_bl31_params = bl2_plat_get_bl31_params();
bl2_to_bl31_plat_params = bl2_plat_get_bl31_plat_params();
bl31_ep_info = bl2_plat_get_bl31_ep_info();
/*
@ -116,16 +116,10 @@ void bl2_main(void)
bl2_plat_set_bl31_ep_info(bl2_to_bl31_params->bl31_image_info,
bl31_ep_info);
/*
* Create a new layout of memory for BL31 as seen by BL2. This
* will gobble up all the BL2 memory.
*/
init_bl31_mem_layout(bl2_tzram_layout,
&bl2_to_bl31_plat_params->bl31_meminfo,
bl31_load);
bl2_plat_get_bl33_meminfo(&bl33_mem_info);
/* Load the BL33 image in non-secure memory provided by the platform */
e = load_image(&bl2_to_bl31_plat_params->bl33_meminfo,
e = load_image(&bl33_mem_info,
BL33_IMAGE_NAME,
BOT_LOAD,
plat_get_ns_image_entrypoint(),
@ -147,10 +141,11 @@ void bl2_main(void)
* completely different memory. A zero size indicates that the
* platform does not want to load a BL32 image.
*/
if (bl2_to_bl31_plat_params->bl32_meminfo.total_size) {
e = load_image(&bl2_to_bl31_plat_params->bl32_meminfo,
bl2_plat_get_bl32_meminfo(&bl32_mem_info);
if (bl32_mem_info.total_size) {
e = load_image(&bl32_mem_info,
BL32_IMAGE_NAME,
bl2_to_bl31_plat_params->bl32_meminfo.attr &
bl32_mem_info.attr &
LOAD_MASK,
BL32_BASE,
bl2_to_bl31_params->bl32_image_info,
@ -166,12 +161,10 @@ void bl2_main(void)
}
}
/*
* Run BL31 via an SMC to BL1. Information on how to pass control to
* the BL32 (if present) and BL33 software images will be passed to
* BL31 as an argument.
*/
bl2_run_bl31(bl31_ep_info, (unsigned long)bl2_to_bl31_params,
(unsigned long)bl2_to_bl31_plat_params);
bl2_run_bl31(bl31_ep_info, (unsigned long)bl2_to_bl31_params, 0);
}

9
bl31/bl31_main.c
View File

@ -43,7 +43,7 @@
* for SP execution. In cases where both SPD and SP are absent, or when SPD
* finds it impossible to execute SP, this pointer is left as NULL
******************************************************************************/
static int32_t (*bl32_init)(meminfo_t *);
static int32_t (*bl32_init)(void);
/*******************************************************************************
* Variable to indicate whether next image to execute after BL31 is BL33
@ -114,11 +114,10 @@ void bl31_main(void)
*/
/*
* If SPD had registerd an init hook, invoke it. Pass it the information
* about memory extents
* If SPD had registerd an init hook, invoke it.
*/
if (bl32_init)
(*bl32_init)(bl31_plat_get_bl32_mem_layout());
(*bl32_init)();
/*
* We are ready to enter the next EL. Prepare entry into the image
@ -189,7 +188,7 @@ void bl31_prepare_next_image_entry()
* This function initializes the pointer to BL32 init function. This is expected
* to be called by the SPD after it finishes all its initialization
******************************************************************************/
void bl31_register_bl32_init(int32_t (*func)(meminfo_t *))
void bl31_register_bl32_init(int32_t (*func)(void))
{
bl32_init = func;
}

12
bl32/tsp/aarch64/tsp_entrypoint.S
View File

@ -55,16 +55,6 @@
func tsp_entrypoint
/*---------------------------------------------
* Store the extents of the tzram available to
* BL32 for future use.
* TODO: We are assuming that x9-x10 will not be
* corrupted by any function before platform
* setup.
* ---------------------------------------------
*/
mov x9, x0
mov x10, x1
/* ---------------------------------------------
* The entrypoint is expected to be executed
@ -119,8 +109,6 @@ func tsp_entrypoint
* specific early arch. setup e.g. mmu setup
* ---------------------------------------------
*/
mov x0, x9
mov x1, x10
bl bl32_early_platform_setup
bl bl32_plat_arch_setup

27
bl32/tsp/tsp_main.c
View File

@ -37,6 +37,13 @@
#include <stdio.h>
#include <tsp.h>
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
extern unsigned long __RO_START__;
extern unsigned long __COHERENT_RAM_END__;
/*******************************************************************************
* Lock to control access to the console
******************************************************************************/
@ -66,6 +73,15 @@ static const entry_info_t tsp_entry_info = {
tsp_cpu_suspend_entry,
};
/*******************************************************************************
* The BL32 memory footprint starts with an RO sections and ends
* with a section for coherent RAM. Use it to find the memory size
******************************************************************************/
#define BL32_TOTAL_BASE (unsigned long)(&__RO_START__)
#define BL32_TOTAL_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
static tsp_args_t *set_smc_args(uint64_t arg0,
uint64_t arg1,
uint64_t arg2,
@ -107,10 +123,6 @@ uint64_t tsp_main(void)
uint64_t mpidr = read_mpidr();
uint32_t linear_id = platform_get_core_pos(mpidr);
#if DEBUG
meminfo_t *mem_layout = bl32_plat_sec_mem_layout();
#endif
/* Initialize the platform */
bl32_platform_setup();
@ -123,10 +135,9 @@ uint64_t tsp_main(void)
spin_lock(&console_lock);
printf("TSP %s\n\r", build_message);
INFO("Total memory base : 0x%x\n", mem_layout->total_base);
INFO("Total memory size : 0x%x bytes\n", mem_layout->total_size);
INFO("Free memory base : 0x%x\n", mem_layout->free_base);
INFO("Free memory size : 0x%x bytes\n", mem_layout->free_size);
INFO("Total memory base : 0x%x\n", (unsigned long)BL32_TOTAL_BASE);
INFO("Total memory size : 0x%x bytes\n",
(unsigned long)(BL32_TOTAL_LIMIT - BL32_TOTAL_BASE));
INFO("cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr,
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count,

61
common/bl_common.c
View File

@ -74,67 +74,10 @@ void change_security_state(unsigned int target_security_state)
/*******************************************************************************
* The next two functions are the weak definitions. Platform specific
* code can override them if it wishes to.
* The next function is a weak definition. Platform specific
* code can override it if it wishes to.
******************************************************************************/
/*******************************************************************************
* Function that takes a memory layout into which BL31 has been either top or
* bottom loaded. Using this information, it populates bl31_mem_layout to tell
* BL31 how much memory it has access to and how much is available for use. It
* does not need the address where BL31 has been loaded as BL31 will reclaim
* all the memory used by BL2.
* TODO: Revisit if this and init_bl2_mem_layout can be replaced by a single
* routine.
******************************************************************************/
void init_bl31_mem_layout(const meminfo_t *bl2_mem_layout,
meminfo_t *bl31_mem_layout,
unsigned int load_type)
{
if (load_type == BOT_LOAD) {
/*
* ------------ ^
* | BL2 | |
* |----------| ^ | BL2
* | | | BL2 free | total
* | | | size | size
* |----------| BL2 free base v |
* | BL31 | |
* ------------ BL2 total base v
*/
unsigned long bl31_size;
bl31_mem_layout->free_base = bl2_mem_layout->free_base;
bl31_size = bl2_mem_layout->free_base - bl2_mem_layout->total_base;
bl31_mem_layout->free_size = bl2_mem_layout->total_size - bl31_size;
} else {
/*
* ------------ ^
* | BL31 | |
* |----------| ^ | BL2
* | | | BL2 free | total
* | | | size | size
* |----------| BL2 free base v |
* | BL2 | |
* ------------ BL2 total base v
*/
unsigned long bl2_size;
bl31_mem_layout->free_base = bl2_mem_layout->total_base;
bl2_size = bl2_mem_layout->free_base - bl2_mem_layout->total_base;
bl31_mem_layout->free_size = bl2_mem_layout->free_size + bl2_size;
}
bl31_mem_layout->total_base = bl2_mem_layout->total_base;
bl31_mem_layout->total_size = bl2_mem_layout->total_size;
bl31_mem_layout->attr = load_type;
flush_dcache_range((unsigned long) bl31_mem_layout, sizeof(meminfo_t));
return;
}
/*******************************************************************************
* Function that takes a memory layout into which BL2 has been either top or
* bottom loaded along with the address where BL2 has been loaded in it. Using

5
include/bl2/bl2.h
View File

@ -55,11 +55,6 @@ extern struct meminfo *bl2_plat_sec_mem_layout(void);
******************************************************************************/
extern struct bl31_params *bl2_plat_get_bl31_params(void);
/*******************************************************************************
* This function returns a pointer to the shared memory that the platform has
* kept aside to pass platform related information that BL3-1 could need
******************************************************************************/
extern struct bl31_plat_params *bl2_plat_get_bl31_plat_params(void);
/*******************************************************************************
* This function returns a pointer to the shared memory that the platform

7
include/bl31/bl31.h
View File

@ -43,6 +43,7 @@ extern unsigned long bl31_entrypoint;
*****************************************/
struct meminfo;
struct entry_point_info;
struct bl31_parms;
/*******************************************************************************
* Function prototypes
@ -53,9 +54,9 @@ extern void bl31_set_next_image_type(uint32_t type);
extern uint32_t bl31_get_next_image_type(void);
extern void bl31_prepare_next_image_entry();
extern struct entry_point_info *bl31_get_next_image_info(uint32_t type);
extern void bl31_early_platform_setup(struct bl31_params *from_bl2,
void *plat_params_from_bl2);
extern void bl31_platform_setup(void);
extern struct meminfo *bl31_plat_get_bl32_mem_layout(void);
extern struct meminfo *bl31_plat_sec_mem_layout(void);
extern void bl31_register_bl32_init(int32_t (*)(struct meminfo *));
extern void bl31_register_bl32_init(int32_t (*)(void));
#endif /* __BL31_H__ */

12
include/common/bl_common.h
View File

@ -173,18 +173,6 @@ typedef struct bl31_params {
} bl31_params_t;
/***************************************************************************
* This structure provides platform specific data that needs to be known to
* BL31. Currently, The loader updates the memory information available for
* each binary
***************************************************************************/
typedef struct bl31_plat_params {
meminfo_t bl31_meminfo;
meminfo_t bl32_meminfo;
meminfo_t bl33_meminfo;
} bl31_plat_params_t;
/*
* Compile time assertions related to the 'entry_point_info' structure to
* ensure that the assembler and the compiler view of the offsets of

7
plat/fvp/aarch64/plat_common.c
View File

@ -130,14 +130,15 @@ const mmap_region_t fvp_mmap[] = {
* the platform memory map & initialize the mmu, for the given exception level
******************************************************************************/
#define DEFINE_CONFIGURE_MMU_EL(_el) \
void configure_mmu_el##_el(meminfo_t *mem_layout, \
void configure_mmu_el##_el(unsigned long total_base, \
unsigned long total_size, \
unsigned long ro_start, \
unsigned long ro_limit, \
unsigned long coh_start, \
unsigned long coh_limit) \
{ \
mmap_add_region(mem_layout->total_base, \
mem_layout->total_size, \
mmap_add_region(total_base, \
total_size, \
MT_MEMORY | MT_RW | MT_SECURE); \
mmap_add_region(ro_start, ro_limit - ro_start, \
MT_MEMORY | MT_RO | MT_SECURE); \

3
plat/fvp/bl1_plat_setup.c
View File

@ -138,7 +138,8 @@ void bl1_plat_arch_setup(void)
cci_enable_coherency(read_mpidr());
}
configure_mmu_el3(&bl1_tzram_layout,
configure_mmu_el3(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
TZROM_BASE,
TZROM_BASE + TZROM_SIZE,
BL1_COHERENT_RAM_BASE,

67
plat/fvp/bl2_plat_setup.c
View File

@ -78,7 +78,6 @@ __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
* to BL31
******************************************************************************/
static bl31_params_t *bl2_to_bl31_params;
static bl31_plat_params_t *bl2_to_bl31_plat_params;
static entry_point_info_t *bl31_ep_info;
meminfo_t *bl2_plat_sec_mem_layout(void)
@ -116,9 +115,6 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
bl2_to_bl31_params = &bl31_params_mem->bl31_params;
SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
/* Assign memory for platform specific information */
bl2_to_bl31_plat_params = &bl31_params_mem->bl31_plat_params;
/* Fill BL31 related information */
bl31_ep_info = &bl31_params_mem->bl31_ep_info;
bl2_to_bl31_params->bl31_image_info = &bl31_params_mem->bl31_image_info;
@ -136,18 +132,6 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info,
PARAM_IMAGE_BINARY,
VERSION_1, 0);
/*
* Populate the extents of memory available for loading BL32.
* TODO: We are temporarily executing BL2 from TZDRAM;
* will eventually move to Trusted SRAM
*/
bl2_to_bl31_plat_params->bl32_meminfo.total_base = BL32_BASE;
bl2_to_bl31_plat_params->bl32_meminfo.free_base = BL32_BASE;
bl2_to_bl31_plat_params->bl32_meminfo.total_size =
(TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
bl2_to_bl31_plat_params->bl32_meminfo.free_size =
(TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
bl2_to_bl31_plat_params->bl32_meminfo.attr = BOT_LOAD;
}
/* Fill BL33 related information */
@ -157,23 +141,10 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
bl2_to_bl31_params->bl33_image_info = &bl31_params_mem->bl33_image_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
VERSION_1, 0);
/* Populate the extents of memory available for loading BL33 */
bl2_to_bl31_plat_params->bl33_meminfo.total_base = DRAM_BASE;
bl2_to_bl31_plat_params->bl33_meminfo.total_size = DRAM_SIZE;
bl2_to_bl31_plat_params->bl33_meminfo.free_base = DRAM_BASE;
bl2_to_bl31_plat_params->bl33_meminfo.free_size = DRAM_SIZE;
return bl2_to_bl31_params;
}
/*******************************************************************************
* This function returns a pointer to the memory that the platform has kept
* aside to pass platform related information that BL31 could need
******************************************************************************/
bl31_plat_params_t *bl2_plat_get_bl31_plat_params(void)
{
return bl2_to_bl31_plat_params;
}
/*******************************************************************************
* This function returns a pointer to the shared memory that the platform
@ -239,7 +210,8 @@ void bl2_plat_flush_bl31_params(void)
******************************************************************************/
void bl2_plat_arch_setup()
{
configure_mmu_el1(&bl2_tzram_layout,
configure_mmu_el1(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL2_RO_BASE,
BL2_RO_LIMIT,
BL2_COHERENT_RAM_BASE,
@ -308,3 +280,38 @@ void bl2_plat_set_bl33_ep_info(image_info_t *image,
DISABLE_ALL_EXCEPTIONS);
SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
}
/*******************************************************************************
* Populate the extents of memory available for loading BL32
******************************************************************************/
void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
{
/*
* Populate the extents of memory available for loading BL32.
* TODO: We are temporarily executing BL2 from TZDRAM;
* will eventually move to Trusted SRAM
*/
bl32_meminfo->total_base = BL32_BASE;
bl32_meminfo->free_base = BL32_BASE;
bl32_meminfo->total_size =
(TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
bl32_meminfo->free_size =
(TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
bl32_meminfo->attr = BOT_LOAD;
bl32_meminfo->next = 0;
}
/*******************************************************************************
* Populate the extents of memory available for loading BL33
******************************************************************************/
void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
{
bl33_meminfo->total_base = DRAM_BASE;
bl33_meminfo->total_size = DRAM_SIZE;
bl33_meminfo->free_base = DRAM_BASE;
bl33_meminfo->free_size = DRAM_SIZE;
bl33_meminfo->attr = 0;
bl33_meminfo->attr = 0;
}

18
plat/fvp/bl31_plat_setup.c
View File

@ -72,17 +72,6 @@ extern unsigned long __COHERENT_RAM_END__;
* BL31 from BL2.
******************************************************************************/
static bl31_params_t *bl2_to_bl31_params;
static bl31_plat_params_t *bl2_to_bl31_plat_params;
meminfo_t *bl31_plat_sec_mem_layout(void)
{
return &bl2_to_bl31_plat_params->bl31_meminfo;
}
meminfo_t *bl31_plat_get_bl32_mem_layout(void)
{
return &bl2_to_bl31_plat_params->bl32_meminfo;
}
/*******************************************************************************
* Return a pointer to the 'entry_point_info' structure of the next image for the
@ -117,14 +106,12 @@ entry_point_info_t *bl31_get_next_image_info(uint32_t type)
* data
******************************************************************************/
void bl31_early_platform_setup(bl31_params_t *from_bl2,
bl31_plat_params_t *plat_info_from_bl2)
void *plat_params_from_bl2)
{
assert(from_bl2->h.type == PARAM_BL31);
assert(from_bl2->h.version >= VERSION_1);
bl2_to_bl31_params = from_bl2;
bl2_to_bl31_plat_params = plat_info_from_bl2;
/* Initialize the console to provide early debug support */
console_init(PL011_UART0_BASE);
@ -179,7 +166,8 @@ void bl31_platform_setup()
******************************************************************************/
void bl31_plat_arch_setup()
{
configure_mmu_el3(&bl2_to_bl31_plat_params->bl31_meminfo,
configure_mmu_el3(TZRAM_BASE,
TZRAM_SIZE,
BL31_RO_BASE,
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,

29
plat/fvp/bl32_plat_setup.c
View File

@ -63,38 +63,16 @@ extern unsigned long __COHERENT_RAM_END__;
#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
/* Data structure which holds the extents of the trusted SRAM for BL32 */
static meminfo_t bl32_tzdram_layout
__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
section("tzfw_coherent_mem")));
meminfo_t *bl32_plat_sec_mem_layout(void)
{
return &bl32_tzdram_layout;
}
/*******************************************************************************
* BL1 has passed the extents of the trusted SRAM that's at BL32's disposal.
* Initialize the BL32 data structure with the memory extends and initialize
* the UART
* Initialize the UART
******************************************************************************/
void bl32_early_platform_setup(meminfo_t *mem_layout,
void *data)
void bl32_early_platform_setup(void)
{
/*
* Initialize a different console than already in use to display
* messages from TSP
*/
console_init(PL011_UART1_BASE);
/* Setup the BL32 memory layout */
bl32_tzdram_layout.total_base = mem_layout->total_base;
bl32_tzdram_layout.total_size = mem_layout->total_size;
bl32_tzdram_layout.free_base = mem_layout->free_base;
bl32_tzdram_layout.free_size = mem_layout->free_size;
bl32_tzdram_layout.attr = mem_layout->attr;
bl32_tzdram_layout.next = 0;
}
/*******************************************************************************
@ -111,7 +89,8 @@ void bl32_platform_setup()
******************************************************************************/
void bl32_plat_arch_setup()
{
configure_mmu_el1(&bl32_tzdram_layout,
configure_mmu_el1(BL32_RO_BASE,
(BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
BL32_RO_BASE,
BL32_RO_LIMIT,
BL32_COHERENT_RAM_BASE,

16
plat/fvp/platform.h
View File

@ -356,7 +356,6 @@ typedef volatile struct mailbox {
struct plat_pm_ops;
struct meminfo;
struct bl31_params;
struct bl31_plat_params;
struct image_info;
struct entry_point_info;
@ -364,11 +363,10 @@ struct entry_point_info;
/*******************************************************************************
* This structure represents the superset of information that is passed to
* BL31 e.g. while passing control to it from BL2 which is bl31_params
* and bl31_plat_params and its elements
* and another platform specific params
******************************************************************************/
typedef struct bl2_to_bl31_params_mem {
struct bl31_params bl31_params;
struct bl31_plat_params bl31_plat_params;
struct image_info bl31_image_info;
struct image_info bl32_image_info;
struct image_info bl33_image_info;
@ -401,12 +399,14 @@ extern int platform_setup_pm(const struct plat_pm_ops **);
extern unsigned int platform_get_core_pos(unsigned long mpidr);
extern void enable_mmu_el1(void);
extern void enable_mmu_el3(void);
extern void configure_mmu_el1(struct meminfo *mem_layout,
extern void configure_mmu_el1(unsigned long total_base,
unsigned long total_size,
unsigned long ro_start,
unsigned long ro_limit,
unsigned long coh_start,
unsigned long coh_limit);
extern void configure_mmu_el3(struct meminfo *mem_layout,
extern void configure_mmu_el3(unsigned long total_base,
unsigned long total_size,
unsigned long ro_start,
unsigned long ro_limit,
unsigned long coh_start,
@ -474,6 +474,12 @@ extern void bl2_plat_set_bl32_ep_info(struct image_info *image,
extern void bl2_plat_set_bl33_ep_info(struct image_info *image,
struct entry_point_info *ep);
/* Gets the memory layout for BL32 */
extern void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info);
/* Gets the memory layout for BL33 */
extern void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info);
#endif /*__ASSEMBLY__*/

19
services/spd/tspd/tspd_main.c
View File

@ -66,7 +66,7 @@ DEFINE_SVC_UUID(tsp_uuid,
0x5b3056a0, 0x3291, 0x427b, 0x98, 0x11,
0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa);
int32_t tspd_init(meminfo_t *bl32_meminfo);
int32_t tspd_init(void);
/*******************************************************************************
@ -126,28 +126,15 @@ int32_t tspd_setup(void)
* It also assumes that a valid non-secure context has been initialised by PSCI
* so it does not need to save and restore any non-secure state. This function
* performs a synchronous entry into the Secure payload. The SP passes control
* back to this routine through a SMC. It also passes the extents of memory made
* available to BL32 by BL31.
* back to this routine through a SMC.
******************************************************************************/
int32_t tspd_init(meminfo_t *bl32_meminfo)
int32_t tspd_init(void)
{
uint64_t mpidr = read_mpidr();
uint32_t linear_id = platform_get_core_pos(mpidr);
uint64_t rc;
tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
/*
* Arrange for passing a pointer to the meminfo structure
* describing the memory extents available to the secure
* payload.
* TODO: We are passing a pointer to BL31 internal memory
* whereas this structure should be copied to a communication
* buffer between the SP and SPD.
*/
write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx),
CTX_GPREG_X0,
(uint64_t) bl32_meminfo);
/*
* Arrange for an entry into the test secure payload. We expect an array
* of vectors in return