Tegra186: read activity monitor's clock counter values
This patch adds a new SMC function ID to read the refclk and coreclk clock counter values from the Activity Monitor. The non-secure world requires this information to calculate the CPU's frequency. Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq" The following CPU registers have to be set by the non-secure driver before issuing the SMC: X1 = MPIDR of the target core X2 = MIDR of the target core Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -261,10 +261,16 @@
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#define SECURE_SCRATCH_RSV55_HI 0x80C
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#define SECURE_SCRATCH_RSV55_HI 0x80C
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/*******************************************************************************
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/*******************************************************************************
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* Tegra Memory Mapped Control Register Access Bus constants
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* Tegra Memory Mapped Control Register Access constants
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******************************************************************************/
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******************************************************************************/
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#define TEGRA_MMCRAB_BASE 0x0E000000
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#define TEGRA_MMCRAB_BASE 0x0E000000
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/*******************************************************************************
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* Tegra Memory Mapped Activity Monitor Register Access constants
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******************************************************************************/
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#define TEGRA_ARM_ACTMON_CTR_BASE 0x0E060000
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#define TEGRA_DENVER_ACTMON_CTR_BASE 0x0E070000
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/*******************************************************************************
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/*******************************************************************************
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* Tegra SMMU Controller constants
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* Tegra SMMU Controller constants
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******************************************************************************/
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******************************************************************************/
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@ -102,6 +102,8 @@ static const mmap_region_t tegra_mmap[] = {
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MT_DEVICE | MT_RW | MT_SECURE),
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
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MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */
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MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MT_DEVICE | MT_RW | MT_SECURE),
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{0}
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{0}
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@ -34,6 +34,7 @@
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#include <bl_common.h>
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#include <bl_common.h>
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#include <context_mgmt.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <debug.h>
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#include <denver.h>
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#include <errno.h>
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#include <errno.h>
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#include <mce.h>
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#include <mce.h>
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#include <memctrl.h>
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#include <memctrl.h>
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@ -43,11 +44,16 @@
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extern uint32_t tegra186_system_powerdn_state;
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extern uint32_t tegra186_system_powerdn_state;
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/*******************************************************************************
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* Offset to read the ref_clk counter value
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******************************************************************************/
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#define REF_CLK_OFFSET 4
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/*******************************************************************************
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/*******************************************************************************
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* Tegra186 SiP SMCs
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* Tegra186 SiP SMCs
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******************************************************************************/
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******************************************************************************/
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#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
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#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0x82FFFE01
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#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0x82FFFE01
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#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0x82FFFE02
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#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0x82FFFF00
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#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0x82FFFF00
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#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0x82FFFF01
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#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0x82FFFF01
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#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0x82FFFF02
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#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0x82FFFF02
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@ -81,6 +87,8 @@ int plat_sip_handler(uint32_t smc_fid,
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uint64_t flags)
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uint64_t flags)
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{
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{
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int mce_ret;
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int mce_ret;
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int impl, cpu;
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uint32_t base, core_clk_ctr, ref_clk_ctr;
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switch (smc_fid) {
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switch (smc_fid) {
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@ -143,6 +151,36 @@ int plat_sip_handler(uint32_t smc_fid,
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return 0;
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return 0;
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/*
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* This function ID reads the Activity monitor's core/ref clock
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* counter values for a core/cluster.
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*
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* x1 = MPIDR of the target core
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* x2 = MIDR of the target core
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*/
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case TEGRA_SIP_GET_ACTMON_CLK_COUNTERS:
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cpu = (uint32_t)x1 & MPIDR_CPU_MASK;
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impl = ((uint32_t)x2 >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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/* sanity check target CPU number */
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if (cpu > PLATFORM_MAX_CPUS_PER_CLUSTER)
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return -EINVAL;
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/* get the base address for the current CPU */
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base = (impl == DENVER_IMPL) ? TEGRA_DENVER_ACTMON_CTR_BASE :
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TEGRA_ARM_ACTMON_CTR_BASE;
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/* read the clock counter values */
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core_clk_ctr = mmio_read_32(base + (8 * cpu));
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ref_clk_ctr = mmio_read_32(base + (8 * cpu) + REF_CLK_OFFSET);
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/* return the counter values as two different parameters */
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, core_clk_ctr);
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, ref_clk_ctr);
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return 0;
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default:
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default:
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break;
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break;
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}
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}
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@ -57,10 +57,10 @@ $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
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PLATFORM_MAX_CPUS_PER_CLUSTER := 4
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PLATFORM_MAX_CPUS_PER_CLUSTER := 4
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$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
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$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
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MAX_XLAT_TABLES := 20
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MAX_XLAT_TABLES := 24
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$(eval $(call add_define,MAX_XLAT_TABLES))
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$(eval $(call add_define,MAX_XLAT_TABLES))
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MAX_MMAP_REGIONS := 20
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MAX_MMAP_REGIONS := 24
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$(eval $(call add_define,MAX_MMAP_REGIONS))
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$(eval $(call add_define,MAX_MMAP_REGIONS))
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# platform files
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# platform files
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