amlogic: Move SCPI code to common directory
The SCPI code is the same between GXBB and GXL. No need to have it replicated for each SoCs. Move it to the common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I7e416caf1e9538b3ce7702c0363ee00a054e2451
This commit is contained in:
Carlo Caione
parent
01b2a7fc32
commit
69b315aabf
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@ -1,17 +1,17 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <crypto/sha_dma.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <string.h>
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#include <crypto/sha_dma.h>
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#include "gxl_private.h"
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#include "aml_private.h"
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#define SIZE_SHIFT 20
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#define SIZE_MASK 0x1FF
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@ -0,0 +1,40 @@
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef GXBB_PRIVATE_H
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#define GXBB_PRIVATE_H
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#include <stddef.h>
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#include <stdint.h>
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/* Utility functions */
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unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr);
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void gxbb_console_init(void);
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void gxbb_setup_page_tables(void);
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/* MHU functions */
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void mhu_secure_message_start(void);
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void mhu_secure_message_send(uint32_t msg);
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uint32_t mhu_secure_message_wait(void);
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void mhu_secure_message_end(void);
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void mhu_secure_init(void);
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/* SCPI functions */
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void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
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uint32_t cluster_state, uint32_t css_state);
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uint32_t scpi_sys_power_state(uint64_t system_state);
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void scpi_jtag_set_state(uint32_t state, uint8_t select);
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uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size);
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void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
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uint32_t arg2, uint32_t arg3);
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void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send);
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/* Peripherals */
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void gxbb_thermal_unknown(void);
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uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size);
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uint64_t gxbb_efuse_user_max(void);
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#endif /* GXBB_PRIVATE_H */
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@ -1,139 +0,0 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <platform_def.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include "gxbb_private.h"
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#define SIZE_SHIFT 20
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#define SIZE_MASK 0x1FF
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/*
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* Note: The Amlogic SCP firmware uses the legacy SCPI protocol.
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*/
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#define SCPI_CMD_SET_CSS_POWER_STATE 0x04
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#define SCPI_CMD_SET_SYS_POWER_STATE 0x08
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#define SCPI_CMD_JTAG_SET_STATE 0xC0
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#define SCPI_CMD_EFUSE_READ 0xC2
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static inline uint32_t scpi_cmd(uint32_t command, uint32_t size)
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{
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return command | (size << SIZE_SHIFT);
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}
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void scpi_secure_message_send(uint32_t command, uint32_t size)
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{
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mhu_secure_message_send(scpi_cmd(command, size));
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}
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uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out)
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{
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uint32_t response = mhu_secure_message_wait();
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size_t size = (response >> SIZE_SHIFT) & SIZE_MASK;
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response &= ~(SIZE_MASK << SIZE_SHIFT);
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if (size_out != NULL)
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*size_out = size;
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if (message_out != NULL)
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*message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD;
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return response;
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}
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void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
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uint32_t cluster_state, uint32_t css_state)
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{
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uint32_t state = (mpidr & 0x0F) | /* CPU ID */
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((mpidr & 0xF00) >> 4) | /* Cluster ID */
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(cpu_state << 8) |
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(cluster_state << 12) |
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(css_state << 16);
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mhu_secure_message_start();
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mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state);
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mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4));
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mhu_secure_message_wait();
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mhu_secure_message_end();
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}
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uint32_t scpi_sys_power_state(uint64_t system_state)
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{
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uint32_t *response;
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size_t size;
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mhu_secure_message_start();
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mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state);
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mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1));
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scpi_secure_message_receive((void *)&response, &size);
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mhu_secure_message_end();
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return *response;
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}
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void scpi_jtag_set_state(uint32_t state, uint8_t select)
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{
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assert(state <= GXBB_JTAG_STATE_OFF);
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if (select > GXBB_JTAG_A53_EE) {
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WARN("BL31: Invalid JTAG select (0x%x).\n", select);
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return;
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}
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mhu_secure_message_start();
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mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD,
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(state << 8) | (uint32_t)select);
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mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4));
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mhu_secure_message_wait();
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mhu_secure_message_end();
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}
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uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size)
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{
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uint32_t *response;
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size_t resp_size;
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if (size > 0x1FC)
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return 0;
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mhu_secure_message_start();
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mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base);
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mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size);
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mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8));
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scpi_secure_message_receive((void *)&response, &resp_size);
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mhu_secure_message_end();
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/*
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* response[0] is the size of the response message.
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* response[1 ... N] are the contents.
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*/
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if (*response != 0)
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memcpy(dst, response + 1, *response);
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return *response;
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}
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void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
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uint32_t arg2, uint32_t arg3)
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{
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mhu_secure_message_start();
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mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0);
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mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1);
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mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2);
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mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3);
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mhu_secure_message_send(scpi_cmd(0xC3, 16));
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mhu_secure_message_wait();
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mhu_secure_message_end();
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}
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@ -10,7 +10,9 @@ AML_PLAT := plat/amlogic
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AML_PLAT_SOC := ${AML_PLAT}/${PLAT}
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AML_PLAT_COMMON := ${AML_PLAT}/common
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PLAT_INCLUDES := -I${AML_PLAT_SOC}/include
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PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \
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-I${AML_PLAT_SOC}/include \
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-I${AML_PLAT_COMMON}/include
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GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_main.c \
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@ -29,7 +31,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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${AML_PLAT_SOC}/gxbb_efuse.c \
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${AML_PLAT_SOC}/gxbb_mhu.c \
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${AML_PLAT_SOC}/gxbb_pm.c \
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${AML_PLAT_SOC}/gxbb_scpi.c \
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${AML_PLAT_COMMON}/aml_scpi.c \
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${AML_PLAT_SOC}/gxbb_sip_svc.c \
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${AML_PLAT_SOC}/gxbb_thermal.c \
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${GIC_SOURCES}
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@ -14,7 +14,8 @@ DOIMAGEPATH ?= tools/amlogic
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DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage
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PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \
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-I${AML_PLAT_SOC}/include
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-I${AML_PLAT_SOC}/include \
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-I${AML_PLAT_COMMON}/include
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GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_main.c \
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@ -33,7 +34,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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${AML_PLAT_SOC}/gxl_efuse.c \
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${AML_PLAT_SOC}/gxl_mhu.c \
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${AML_PLAT_SOC}/gxl_pm.c \
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${AML_PLAT_SOC}/gxl_scpi.c \
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${AML_PLAT_COMMON}/aml_scpi.c \
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${AML_PLAT_SOC}/gxl_sip_svc.c \
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${AML_PLAT_SOC}/gxl_thermal.c \
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drivers/amlogic/crypto/sha_dma.c \
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