tc0: update GICR base address
The number of ITS have changed from 4 to 1, resulting in GICR base address change. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -236,7 +236,7 @@
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ranges;
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ranges;
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interrupt-controller;
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interrupt-controller;
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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<0x0 0x30140000 0 0x200000>; /* GICR */
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<0x0 0x30080000 0 0x200000>; /* GICR */
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interrupts = <0x1 0x9 0x4>;
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interrupts = <0x1 0x9 0x4>;
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};
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};
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/*
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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/* GIC related constants */
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE UL(0x30000000)
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#define PLAT_ARM_GICD_BASE UL(0x30000000)
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#define PLAT_ARM_GICC_BASE UL(0x2C000000)
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#define PLAT_ARM_GICC_BASE UL(0x2C000000)
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#define PLAT_ARM_GICR_BASE UL(0x30140000)
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#define PLAT_ARM_GICR_BASE UL(0x30080000)
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/*
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/*
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* PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
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* PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
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