From 6a14ac780f182a045783d35199a9ca6f71ccc49b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Wed, 8 Dec 2021 01:27:38 +0100 Subject: [PATCH] refactor(drivers/marvell/comphy-3700): rename Reset and Clock Control register constants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The register at offset 0x1C1 is called Reset and Clock Control in functional specification, but we use constant name GLOB_PHY_CTRL0. Rename it to RST_CLK_CTRL instead. Signed-off-by: Marek Behún Change-Id: I5dac8913bd0686d4f5bd74b91cb7d07ba06df72b --- drivers/marvell/comphy/phy-comphy-3700.c | 4 ++-- drivers/marvell/comphy/phy-comphy-3700.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c index 9be210ad7..184421918 100644 --- a/drivers/marvell/comphy/phy-comphy-3700.c +++ b/drivers/marvell/comphy/phy-comphy-3700.c @@ -776,7 +776,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, * 16. Release SW reset */ data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; - usb3_reg_set(reg_base, COMPHY_GLOB_PHY_CTRL0, data, REG_16_BIT_MASK); + usb3_reg_set(reg_base, COMPHY_RST_CLK_CTRL, data, REG_16_BIT_MASK); /* Wait for > 55 us to allow PCLK be enabled */ udelay(PLL_SET_DELAY_US); @@ -885,7 +885,7 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, /* 11. Release SW reset */ data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32; mask = data | SOFT_RESET | MODE_REFDIV_MASK; - reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); + reg_set16(RST_CLK_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); /* Wait for > 55 us to allow PCLK be enabled */ udelay(PLL_SET_DELAY_US); diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h index 19a10aceb..c8ac8d5d5 100644 --- a/drivers/marvell/comphy/phy-comphy-3700.h +++ b/drivers/marvell/comphy/phy-comphy-3700.h @@ -162,8 +162,8 @@ enum { #define LANE_CFG4_ADDR(unit) (COMPHY_LANE_CFG4 * PHY_SHFT(unit)) #define SPREAD_SPECTRUM_CLK_EN BIT(7) -#define COMPHY_GLOB_PHY_CTRL0 0x1C1 -#define GLOB_PHY_CTRL0_ADDR(unit) (COMPHY_GLOB_PHY_CTRL0 * PHY_SHFT(unit)) +#define COMPHY_RST_CLK_CTRL 0x1C1 +#define RST_CLK_CTRL_ADDR(unit) (COMPHY_RST_CLK_CTRL * PHY_SHFT(unit)) #define SOFT_RESET BIT(0) #define MODE_CORE_CLK_FREQ_SEL BIT(9) #define MODE_PIPE_WIDTH_32 BIT(3)