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feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs 

The following SMIDs are disabled by default.

* GICD: MBIST REQ error and GICD FMU ClkGate override
* PPI: MBIST REQ error and PPI FMU ClkGate override
* ITS: MBIST REQ error and ITS FMU ClkGate override

This patch explicitly enables them during the FMU init sequence.

Change-Id: I573e64786e3318d4cbcd07d0a1caf25f8e6e9200
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2022-01-26 00:33:02 -08:00
parent 3f0094c15d
commit 6a1c17c770
2 changed files with 13 additions and 6 deletions
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18
drivers/arm/gic/v3/gic600ae_fmu.c
View File

@ -302,22 +302,26 @@ void gic600_fmu_init(uint64_t base, uint64_t blk_present_mask,
*/
if ((blk_present_mask & BIT(FMU_BLK_GICD)) != 0U) {
smen = (GICD_MBIST_REQ_ERROR << FMU_SMEN_SMID_SHIFT) |
(FMU_BLK_GICD << FMU_SMEN_BLK_SHIFT);
(FMU_BLK_GICD << FMU_SMEN_BLK_SHIFT) |
FMU_SMEN_EN_BIT;
gic_fmu_write_smen(base, smen);
smen = (GICD_FMU_CLKGATE_ERROR << FMU_SMEN_SMID_SHIFT) |
(FMU_BLK_GICD << FMU_SMEN_BLK_SHIFT);
(FMU_BLK_GICD << FMU_SMEN_BLK_SHIFT) |
FMU_SMEN_EN_BIT;
gic_fmu_write_smen(base, smen);
}
for (unsigned int i = FMU_BLK_PPI0; i < FMU_BLK_PPI31; i++) {
if ((blk_present_mask & BIT(i)) != 0U) {
smen = (PPI_MBIST_REQ_ERROR << FMU_SMEN_SMID_SHIFT) |
(i << FMU_SMEN_BLK_SHIFT);
(i << FMU_SMEN_BLK_SHIFT) |
FMU_SMEN_EN_BIT;
gic_fmu_write_smen(base, smen);
smen = (PPI_FMU_CLKGATE_ERROR << FMU_SMEN_SMID_SHIFT) |
(i << FMU_SMEN_BLK_SHIFT);
(i << FMU_SMEN_BLK_SHIFT) |
FMU_SMEN_EN_BIT;
gic_fmu_write_smen(base, smen);
}
}
@ -325,11 +329,13 @@ void gic600_fmu_init(uint64_t base, uint64_t blk_present_mask,
for (unsigned int i = FMU_BLK_ITS0; i < FMU_BLK_ITS7; i++) {
if ((blk_present_mask & BIT(i)) != 0U) {
smen = (ITS_MBIST_REQ_ERROR << FMU_SMEN_SMID_SHIFT) |
(i << FMU_SMEN_BLK_SHIFT);
(i << FMU_SMEN_BLK_SHIFT) |
FMU_SMEN_EN_BIT;
gic_fmu_write_smen(base, smen);
smen = (ITS_FMU_CLKGATE_ERROR << FMU_SMEN_SMID_SHIFT) |
(i << FMU_SMEN_BLK_SHIFT);
(i << FMU_SMEN_BLK_SHIFT) |
FMU_SMEN_EN_BIT;
gic_fmu_write_smen(base, smen);
}
}

1
include/drivers/arm/gic600ae_fmu.h
View File

@ -37,6 +37,7 @@
/* SMEN constants */
#define FMU_SMEN_BLK_SHIFT U(8)
#define FMU_SMEN_SMID_SHIFT U(24)
#define FMU_SMEN_EN_BIT BIT(0)
/* Error record IDs */
#define FMU_BLK_GICD U(0)