From 6a367fd1efb37a02df22b5f8b61a7b3d5c5a12a6 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 8 Jul 2015 13:46:42 +0530 Subject: [PATCH] Tegra: Fix the delay loop used during SC7 exit This patch fixes the delay loop used to wake up the BPMP during SC7 exit. The earlier loop would fail just when the timer was about to wrap-around (e.g. when TEGRA_TMRUS_BASE is 0xfffffffe, the target value becomes 0, which would cause the loop to exit before it's expiry). Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c b/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c index a36cf2d73..b473dd656 100644 --- a/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c +++ b/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -230,10 +231,7 @@ void tegra_fc_reset_bpmp(void) ; /* wait till value reaches EVP_BPMP_RESET_VECTOR */ /* Wait for 2us before de-asserting the reset signal. */ - val = mmio_read_32(TEGRA_TMRUS_BASE); - val += 2; - while (val > mmio_read_32(TEGRA_TMRUS_BASE)) - ; /* wait for 2us */ + udelay(2); /* De-assert BPMP reset */ mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_CLR, CLK_BPMP_RST);