Merge "Tegra194: validate C6 power state type" into integration
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6ac1bb301b
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@ -73,6 +73,11 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state,
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switch (state_id) {
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switch (state_id) {
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case PSTATE_ID_CORE_IDLE:
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case PSTATE_ID_CORE_IDLE:
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if (psci_get_pstate_type(power_state) != PSTATE_TYPE_STANDBY) {
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ret = PSCI_E_INVALID_PARAMS;
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break;
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}
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/* Core idle request */
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/* Core idle request */
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
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req_state->pwr_domain_state[MPIDR_AFFLVL1] = PSCI_LOCAL_STATE_RUN;
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req_state->pwr_domain_state[MPIDR_AFFLVL1] = PSCI_LOCAL_STATE_RUN;
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