Merge changes I16cac81b,I6c709c0c,I69581714,I018d158f,I23146f56, ... into integration
* changes: fix(drivers/marvell/comphy-cp110): fix error code in pcie power on fix(drivers/marvell/comphy-3700): handle failures in power functions fix(drivers/marvell/comphy-3700): fix address overflow refactor(drivers/marvell/comphy-3700): simplify usage of comphy_sgmii_phy_init() refactor(drivers/marvell/comphy-3700): simplify usage of indirect access on lane2 refactor(drivers/marvell/comphy-3700): simplify usage of sata power off
This commit is contained in:
Manish Pandey
TrustedFirmware Code Review
commit
6acaba6238
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@ -118,7 +118,7 @@ static uint16_t sgmii_phy_init[512] = {
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};
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/* PHY selector configures with corresponding modes */
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static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
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static int mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
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uint32_t comphy_mode)
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{
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uint32_t reg;
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@ -168,9 +168,10 @@ static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
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}
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mmio_write_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG, reg);
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return;
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return 0;
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error:
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ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode);
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return -EINVAL;
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}
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/*
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@ -214,7 +215,7 @@ static int mvebu_a3700_comphy_get_mode(uint8_t comphy_index)
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/* It is only used for SATA and USB3 on comphy lane2. */
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static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data,
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uint16_t mask, int mode)
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uint16_t mask, bool is_sata)
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{
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/*
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* When Lane 2 PHY is for USB3, access the PHY registers
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@ -224,27 +225,38 @@ static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data,
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* within the SATA Host Controller registers, Lane 2 base register
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* offset is 0x200
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*/
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if (mode == COMPHY_UNUSED)
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return;
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if (mode == COMPHY_SATA_MODE)
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if (is_sata) {
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mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, offset);
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else
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} else {
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mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET,
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offset + USB3PHY_LANE2_REG_BASE_OFFSET);
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}
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reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask);
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}
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/* It is only used USB3 direct access not on comphy lane2. */
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/* It is only used for SATA on comphy lane2. */
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static void comphy_sata_set_indirect(uintptr_t addr, uint32_t reg_offset,
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uint16_t data, uint16_t mask)
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{
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comphy_set_indirect(addr, reg_offset, data, mask, true);
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}
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/* It is only used for USB3 indirect access on comphy lane2. */
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static void comphy_usb3_set_indirect(uintptr_t addr, uint32_t reg_offset,
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uint16_t data, uint16_t mask)
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{
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comphy_set_indirect(addr, reg_offset, data, mask, false);
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}
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/* It is only used for USB3 direct access not on comphy lane2. */
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static void comphy_usb3_set_direct(uintptr_t addr, uint32_t reg_offset,
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uint16_t data, uint16_t mask, int mode)
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uint16_t data, uint16_t mask)
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{
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reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask);
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}
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static void comphy_sgmii_phy_init(uint32_t comphy_index, uint32_t mode,
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uintptr_t sd_ip_addr)
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static void comphy_sgmii_phy_init(uintptr_t sd_ip_addr, bool is_1gbps)
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{
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const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix);
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int addr, fix_idx;
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@ -259,8 +271,7 @@ static void comphy_sgmii_phy_init(uint32_t comphy_index, uint32_t mode,
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* comparison to 3.125 Gbps values. These register values are
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* stored in "sgmii_phy_init_fix" array.
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*/
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if ((mode != COMPHY_SGMII_MODE) &&
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(sgmii_phy_init_fix[fix_idx].addr == addr)) {
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if (!is_1gbps && sgmii_phy_init_fix[fix_idx].addr == addr) {
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/* Use new value */
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val = sgmii_phy_init_fix[fix_idx].value;
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if (fix_idx < fix_arr_sz)
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@ -276,21 +287,22 @@ static void comphy_sgmii_phy_init(uint32_t comphy_index, uint32_t mode,
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static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
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uint32_t comphy_mode)
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{
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int ret = 0;
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int ret;
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uint32_t offset, data = 0, ref_clk;
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uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG;
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int mode = COMPHY_GET_MODE(comphy_mode);
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int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
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debug_enter();
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/* Configure phy selector for SATA */
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mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode);
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ret = mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode);
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if (ret) {
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return ret;
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}
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/* Clear phy isolation mode to make it work in normal mode */
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offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
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comphy_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE,
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mode);
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comphy_sata_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE);
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/* 0. Check the Polarity invert bits */
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if (invert & COMPHY_POLARITY_TXD_INVERT)
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@ -299,13 +311,13 @@ static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
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data |= RXD_INVERT_BIT;
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offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
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comphy_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT |
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RXD_INVERT_BIT, mode);
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comphy_sata_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT |
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RXD_INVERT_BIT);
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/* 1. Select 40-bit data width width */
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offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET;
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comphy_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT,
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SEL_DATA_WIDTH_MASK, mode);
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comphy_sata_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT,
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SEL_DATA_WIDTH_MASK);
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/* 2. Select reference clock(25M) and PHY mode (SATA) */
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offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
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@ -314,17 +326,17 @@ static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
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else
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ref_clk = REF_CLOCK_SPEED_25M;
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comphy_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA,
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REF_FREF_SEL_MASK | PHY_MODE_MASK, mode);
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comphy_sata_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA,
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REF_FREF_SEL_MASK | PHY_MODE_MASK);
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/* 3. Use maximum PLL rate (no power save) */
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offset = COMPHY_KVCO_CAL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
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comphy_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT,
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USE_MAX_PLL_RATE_BIT, mode);
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comphy_sata_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT,
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USE_MAX_PLL_RATE_BIT);
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/* 4. Reset reserved bit */
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comphy_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0,
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PHYCTRL_FRM_PIN_BIT, mode);
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comphy_sata_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0,
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PHYCTRL_FRM_PIN_BIT);
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/* 5. Set vendor-specific configuration (It is done in sata driver) */
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/* XXX: in U-Boot below sequence was executed in this place, in Linux
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@ -346,17 +358,21 @@ static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
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COMPHY_LANE2_INDIR_DATA_OFFSET,
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PLL_READY_TX_BIT, PLL_READY_TX_BIT,
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COMPHY_PLL_TIMEOUT, REG_32BIT);
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if (ret) {
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return -ETIMEDOUT;
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}
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debug_exit();
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return ret;
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return 0;
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}
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static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
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uint32_t comphy_mode)
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{
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int ret = 0;
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uint32_t mask, data, offset;
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int ret;
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uint32_t mask, data;
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uintptr_t offset;
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uintptr_t sd_ip_addr;
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int mode = COMPHY_GET_MODE(comphy_mode);
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int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
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@ -364,7 +380,10 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
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debug_enter();
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/* Set selector */
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mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode);
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ret = mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode);
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if (ret) {
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return ret;
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}
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/* Serdes IP Base address
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* COMPHY Lane0 -- USB3/GBE1
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@ -481,7 +500,7 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
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debug("Running C-DPI phy init %s mode\n",
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mode == COMPHY_2500BASEX_MODE ? "2G5" : "1G");
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if (get_ref_clk() == 40)
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comphy_sgmii_phy_init(comphy_index, mode, sd_ip_addr);
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comphy_sgmii_phy_init(sd_ip_addr, mode != COMPHY_2500BASEX_MODE);
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/*
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* 14. [Simulation Only] should not be used for real chip.
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@ -525,8 +544,10 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
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PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT,
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PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT,
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COMPHY_PLL_TIMEOUT, REG_32BIT);
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if (ret)
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if (ret) {
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ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index);
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return -ETIMEDOUT;
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}
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/*
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* 19. Set COMPHY input port PIN_TX_IDLE=0
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@ -549,26 +570,29 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
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PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT,
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PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT,
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COMPHY_PLL_TIMEOUT, REG_32BIT);
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if (ret)
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if (ret) {
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ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index);
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return -ETIMEDOUT;
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}
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ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE +
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COMPHY_PHY_STATUS_OFFSET(comphy_index),
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PHY_RX_INIT_DONE_BIT, PHY_RX_INIT_DONE_BIT,
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COMPHY_PLL_TIMEOUT, REG_32BIT);
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if (ret)
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if (ret) {
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ERROR("Failed to init RX of SGMII PHY %d\n", comphy_index);
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return -ETIMEDOUT;
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}
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debug_exit();
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return ret;
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return 0;
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}
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static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index)
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{
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int ret = 0;
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uint32_t mask, data, offset;
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uintptr_t offset;
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uint32_t mask, data;
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debug_enter();
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@ -579,28 +603,31 @@ static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index)
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debug_exit();
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return ret;
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return 0;
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}
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static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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uint32_t comphy_mode)
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{
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int ret = 0;
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int ret;
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uintptr_t reg_base = 0;
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uint32_t mask, data, addr, cfg, ref_clk;
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uintptr_t addr;
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uint32_t mask, data, cfg, ref_clk;
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void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data,
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uint16_t mask, int mode);
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int mode = COMPHY_GET_MODE(comphy_mode);
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uint16_t mask);
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int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
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debug_enter();
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/* Set phy seclector */
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mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode);
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ret = mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode);
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if (ret) {
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return ret;
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}
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/* Set usb3 reg access func, Lane2 is indirect access */
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if (comphy_index == COMPHY_LANE2) {
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usb3_reg_set = &comphy_set_indirect;
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usb3_reg_set = &comphy_usb3_set_indirect;
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reg_base = COMPHY_INDIRECT_REG;
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} else {
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/* Get the direct access register resource and map */
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@ -619,7 +646,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK |
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CFG_TX_ALIGN_POS_MASK;
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usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK,
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mask, mode);
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mask);
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/*
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* 2. Set BIT0: enable transmitter in high impedance mode
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@ -631,20 +658,20 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK |
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TX_ELEC_IDLE_MODE_EN;
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data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;
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usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask, mode);
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usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask);
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/*
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* 3. Set Spread Spectrum Clock Enabled
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*/
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usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR,
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SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN, mode);
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SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN);
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/*
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* 4. Set Override Margining Controls From the MAC:
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* Use margining signals from lane configuration
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*/
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usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR,
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MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK, mode);
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MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK);
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/*
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* 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles
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@ -652,13 +679,13 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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*/
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usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0,
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(MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE |
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BUNDLE_SAMPLE_CTRL | PLL_READY_DLY), mode);
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BUNDLE_SAMPLE_CTRL | PLL_READY_DLY));
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/*
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* 6. Set G2 Spread Spectrum Clock Amplitude at 4K
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*/
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usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2,
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G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK, mode);
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G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK);
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/*
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* 7. Unset G3 Spread Spectrum Clock Amplitude
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@ -667,7 +694,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK |
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RSVD_PH03FH_6_0_MASK;
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usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3,
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G3_VREG_RXTX_MAS_ISET_60U, mask, mode);
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G3_VREG_RXTX_MAS_ISET_60U, mask);
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/*
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* 8. Check crystal jumper setting and program the Power and PLL Control
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@ -688,39 +715,37 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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REF_FREF_SEL_MASK;
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data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
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PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk;
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usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask, mode);
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usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask);
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mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
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CFG_PM_RXDLOZ_WAIT_MASK;
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data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg;
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usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask, mode);
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usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask);
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/*
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* 9. Enable idle sync
|
||||
*/
|
||||
data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN;
|
||||
usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK,
|
||||
mode);
|
||||
usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK);
|
||||
|
||||
/*
|
||||
* 10. Enable the output of 500M clock
|
||||
*/
|
||||
data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN;
|
||||
usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK,
|
||||
mode);
|
||||
usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK);
|
||||
|
||||
/*
|
||||
* 11. Set 20-bit data width
|
||||
*/
|
||||
usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT,
|
||||
REG_16_BIT_MASK, mode);
|
||||
REG_16_BIT_MASK);
|
||||
|
||||
/*
|
||||
* 12. Override Speed_PLL value and use MAC PLL
|
||||
*/
|
||||
usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL,
|
||||
(SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT),
|
||||
REG_16_BIT_MASK, mode);
|
||||
REG_16_BIT_MASK);
|
||||
|
||||
/*
|
||||
* 13. Check the Polarity invert bit
|
||||
|
|
@ -733,27 +758,26 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
|
|||
data |= RXD_INVERT_BIT;
|
||||
}
|
||||
mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
|
||||
usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask, mode);
|
||||
usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask);
|
||||
|
||||
/*
|
||||
* 14. Set max speed generation to USB3.0 5Gbps
|
||||
*/
|
||||
usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_USB3_5G,
|
||||
PHY_GEN_MAX_MASK, mode);
|
||||
PHY_GEN_MAX_MASK);
|
||||
|
||||
/*
|
||||
* 15. Set capacitor value for FFE gain peaking to 0xF
|
||||
*/
|
||||
usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3,
|
||||
COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK,
|
||||
mode);
|
||||
COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK);
|
||||
|
||||
/*
|
||||
* 16. Release SW reset
|
||||
*/
|
||||
data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;
|
||||
usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data,
|
||||
REG_16_BIT_MASK, mode);
|
||||
REG_16_BIT_MASK);
|
||||
|
||||
/* Wait for > 55 us to allow PCLK be enabled */
|
||||
udelay(PLL_SET_DELAY_US);
|
||||
|
|
@ -771,12 +795,14 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
|
|||
TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
|
||||
COMPHY_PLL_TIMEOUT, REG_16BIT);
|
||||
}
|
||||
if (ret)
|
||||
if (ret) {
|
||||
ERROR("Failed to lock USB3 PLL\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
debug_exit();
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
|
||||
|
|
@ -862,12 +888,14 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
|
|||
ret = polling_with_timeout(LANE_STATUS1_ADDR(PCIE) + COMPHY_SD_ADDR,
|
||||
TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
|
||||
COMPHY_PLL_TIMEOUT, REG_16BIT);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
ERROR("Failed to lock PCIE PLL\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
debug_exit();
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode)
|
||||
|
|
@ -919,23 +947,22 @@ static int mvebu_a3700_comphy_usb3_power_off(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int mvebu_a3700_comphy_sata_power_off(uint32_t comphy_mode)
|
||||
static int mvebu_a3700_comphy_sata_power_off(void)
|
||||
{
|
||||
uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG;
|
||||
int mode = COMPHY_GET_MODE(comphy_mode);
|
||||
uint32_t offset;
|
||||
|
||||
debug_enter();
|
||||
|
||||
/* Set phy isolation mode */
|
||||
offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
|
||||
comphy_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE,
|
||||
PHY_ISOLATE_MODE, mode);
|
||||
comphy_sata_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE,
|
||||
PHY_ISOLATE_MODE);
|
||||
|
||||
/* Power off PLL, Tx, Rx */
|
||||
offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
|
||||
comphy_set_indirect(comphy_indir_regs, offset, 0,
|
||||
PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT, mode);
|
||||
comphy_sata_set_indirect(comphy_indir_regs, offset, 0,
|
||||
PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);
|
||||
|
||||
debug_exit();
|
||||
|
||||
|
|
@ -968,7 +995,7 @@ int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode)
|
|||
err = mvebu_a3700_comphy_usb3_power_off();
|
||||
break;
|
||||
case (COMPHY_SATA_MODE):
|
||||
err = mvebu_a3700_comphy_sata_power_off(comphy_mode);
|
||||
err = mvebu_a3700_comphy_sata_power_off();
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -1730,11 +1730,13 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base,
|
|||
HPIPE_LANE_STATUS1_REG;
|
||||
data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
|
||||
mask = data;
|
||||
ret = polling_with_timeout(addr, data, mask,
|
||||
data = polling_with_timeout(addr, data, mask,
|
||||
PLL_LOCK_TIMEOUT,
|
||||
REG_32BIT);
|
||||
if (ret)
|
||||
if (data) {
|
||||
ERROR("Failed to lock PCIE PLL\n");
|
||||
ret = -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue