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Add ISR_EL1 to crash report 

Bring ISR bits definition as a mnemonic for troublershooters as well.

Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
This commit is contained in:
Gerald Lejeune 2016-03-22 11:11:46 +01:00
parent 4ca5753576
commit 6b836cf988
2 changed files with 8 additions and 1 deletions
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4
bl31/aarch64/crash_reporting.S
View File

@ -70,7 +70,8 @@ non_el3_sys_regs:
"tpidrro_el0", "dacr32_el2", "ifsr32_el2", "par_el1",\
"mpidr_el1", "afsr0_el1", "afsr1_el1", "contextidr_el1",\
"vbar_el1", "cntp_ctl_el0", "cntp_cval_el0", "cntv_ctl_el0",\
"cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0", ""
"cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0",\
"isr_el1", ""
panic_msg:
.asciz "PANIC in EL3 at x30 = 0x"
@ -338,6 +339,7 @@ func do_crash_reporting
mrs x8, cntkctl_el1
mrs x9, fpexc32_el2
mrs x10, sp_el0
mrs x11, isr_el1
bl str_in_crash_buf_print
/* Get the cpu specific registers to report */

5
include/lib/aarch64/arch.h
View File

@ -186,6 +186,11 @@
#define HCR_IMO_BIT (1 << 4)
#define HCR_FMO_BIT (1 << 3)
/* ISR definitions */
#define ISR_A_SHIFT 8
#define ISR_I_SHIFT 7
#define ISR_F_SHIFT 6
/* CNTHCTL_EL2 definitions */
#define EVNTEN_BIT (1 << 2)
#define EL1PCEN_BIT (1 << 1)