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fix(drivers/marvell/comphy-3700): fix reference clock selection value names 

The current definitions of reference clock speed register values
  #define PCIE_REF_CLOCK_SPEED_25M       REF_CLOCK_SPEED_30M
  #define USB3_REF_CLOCK_SPEED_25M       REF_CLOCK_SPEED_30M
is ambiguous. The name of the constant implies 25 MHz, but the value
implies 30 MHz, which may make the reader think that the setting has
something to do with both values.

In reality, the values have different tables for SerDes and PCIe/USB3
PHY mode. The value for 25 MHz for PCIe/USB3 mode (0x2) is the value
for 30 MHz for SerDes mode.

Instead of defining the PCIe/USB3 constants relative to SerDes
constants, define them with absolute values, thus making it a little bit
more obvious that different modes have different value tables.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I50c66c6bbe22b9a9bec4685600cb8560524a643c
This commit is contained in:
Marek Behún 2021-12-01 13:23:11 +01:00
parent 9fdecc72f0
commit 6ba97f83db
2 changed files with 13 additions and 14 deletions
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16
drivers/marvell/comphy/phy-comphy-3700.c
View File

@ -322,9 +322,9 @@ static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
/* 2. Select reference clock(25M) and PHY mode (SATA) */
offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
if (get_ref_clk() == 40)
ref_clk = REF_CLOCK_SPEED_40M;
ref_clk = REF_FREF_SEL_SERDES_40MHZ;
else
ref_clk = REF_CLOCK_SPEED_25M;
ref_clk = REF_FREF_SEL_SERDES_25MHZ;
comphy_sata_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA,
REF_FREF_SEL_MASK | PHY_MODE_MASK);
@ -457,9 +457,9 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
* REF_FREF_SEL.
*/
if (get_ref_clk() == 40)
data = REF_CLOCK_SPEED_50M;
data = REF_FREF_SEL_SERDES_50MHZ;
else
data = REF_CLOCK_SPEED_25M;
data = REF_FREF_SEL_SERDES_25MHZ;
mask = REF_FREF_SEL_MASK;
reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask);
@ -701,12 +701,12 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
* accordingly Change RX wait
*/
if (get_ref_clk() == 40) {
ref_clk = REF_CLOCK_SPEED_40M;
ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ;
cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT;
} else {
/* 25 MHz */
ref_clk = USB3_REF_CLOCK_SPEED_25M;
ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ;
cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT;
}
@ -859,9 +859,9 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
*/
if (get_ref_clk() == 40)
ref_clk = REF_CLOCK_SPEED_40M;
ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ;
else
ref_clk = PCIE_REF_CLOCK_SPEED_25M;
ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ;
reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR,
(PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |

11
drivers/marvell/comphy/phy-comphy-3700.h
View File

@ -53,12 +53,11 @@ enum {
#define PLL_LOCK_BIT BIT(8)
#define REF_FREF_SEL_OFFSET 0
#define REF_FREF_SEL_MASK (0x1F << REF_FREF_SEL_OFFSET)
#define REF_CLOCK_SPEED_25M (0x1 << REF_FREF_SEL_OFFSET)
#define REF_CLOCK_SPEED_30M (0x2 << REF_FREF_SEL_OFFSET)
#define PCIE_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
#define USB3_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
#define REF_CLOCK_SPEED_40M (0x3 << REF_FREF_SEL_OFFSET)
#define REF_CLOCK_SPEED_50M (0x4 << REF_FREF_SEL_OFFSET)
#define REF_FREF_SEL_SERDES_25MHZ (0x1 << REF_FREF_SEL_OFFSET)
#define REF_FREF_SEL_SERDES_40MHZ (0x3 << REF_FREF_SEL_OFFSET)
#define REF_FREF_SEL_SERDES_50MHZ (0x4 << REF_FREF_SEL_OFFSET)
#define REF_FREF_SEL_PCIE_USB3_25MHZ (0x2 << REF_FREF_SEL_OFFSET)
#define REF_FREF_SEL_PCIE_USB3_40MHZ (0x3 << REF_FREF_SEL_OFFSET)
#define PHY_MODE_OFFSET 5
#define PHY_MODE_MASK (7 << PHY_MODE_OFFSET)
#define PHY_MODE_SATA (0x0 << PHY_MODE_OFFSET)