From 6c5c5320511ab8202fb9eccce9e66b4e4e0d9a33 Mon Sep 17 00:00:00 2001 From: Lucian Paul-Trifu Date: Fri, 25 Mar 2022 14:30:20 +0000 Subject: [PATCH] feat(smmu): add SMMU abort transaction function Created a function to abort all pending NS DMA transactions to engage complete DMA protection. This call will be used by the subsequent DRTM implementation changes. Signed-off-by: Manish V Badarkhe Signed-off-by: Lucian Paul-Trifu Change-Id: I94992b54c570327d6746295073822a9c0ebdc85d --- drivers/arm/smmu/smmu_v3.c | 27 ++++++++++++++++++++++++++- include/drivers/arm/smmu_v3.h | 7 +++++++ 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/arm/smmu/smmu_v3.c b/drivers/arm/smmu/smmu_v3.c index 45f6df9f1..6c6f978d4 100644 --- a/drivers/arm/smmu/smmu_v3.c +++ b/drivers/arm/smmu/smmu_v3.c @@ -14,7 +14,7 @@ /* SMMU poll number of retries */ #define SMMU_POLL_TIMEOUT_US U(1000) -static int __init smmuv3_poll(uintptr_t smmu_reg, uint32_t mask, +static int smmuv3_poll(uintptr_t smmu_reg, uint32_t mask, uint32_t value) { uint32_t reg_val; @@ -155,3 +155,28 @@ int __init smmuv3_init(uintptr_t smmu_base) return smmuv3_poll(smmu_base + SMMU_S_INIT, SMMU_S_INIT_INV_ALL, 0U); } + +int smmuv3_ns_set_abort_all(uintptr_t smmu_base) +{ + /* Attribute update has completed when SMMU_GBPA.Update bit is 0 */ + if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U) { + return -1; + } + + /* + * Set GBPA's ABORT bit. Other GBPA fields are presumably ignored then, + * so simply preserve their value. + */ + mmio_setbits_32(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE | SMMU_GBPA_ABORT); + if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U) { + return -1; + } + + /* Disable the SMMU to engage the GBPA fields previously configured. */ + mmio_clrbits_32(smmu_base + SMMU_CR0, SMMU_CR0_SMMUEN); + if (smmuv3_poll(smmu_base + SMMU_CR0ACK, SMMU_CR0_SMMUEN, 0U) != 0U) { + return -1; + } + + return 0; +} diff --git a/include/drivers/arm/smmu_v3.h b/include/drivers/arm/smmu_v3.h index e60c75445..37da56f6e 100644 --- a/include/drivers/arm/smmu_v3.h +++ b/include/drivers/arm/smmu_v3.h @@ -12,6 +12,8 @@ #include /* SMMUv3 register offsets from device base */ +#define SMMU_CR0 U(0x0020) +#define SMMU_CR0ACK U(0x0024) #define SMMU_GBPA U(0x0044) #define SMMU_S_IDR1 U(0x8004) #define SMMU_S_INIT U(0x803c) @@ -37,6 +39,9 @@ #endif /* ENABLE_RME */ +/* SMMU_CR0 and SMMU_CR0ACK register fields */ +#define SMMU_CR0_SMMUEN (1UL << 0) + /* SMMU_GBPA register fields */ #define SMMU_GBPA_UPDATE (1UL << 31) #define SMMU_GBPA_ABORT (1UL << 20) @@ -61,4 +66,6 @@ int smmuv3_init(uintptr_t smmu_base); int smmuv3_security_init(uintptr_t smmu_base); +int smmuv3_ns_set_abort_all(uintptr_t smmu_base); + #endif /* SMMU_V3_H */