Merge "drivers: st: clock: register parent of secure clocks" into integration
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
6c71c9bb63
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@ -577,6 +577,43 @@ static const uint8_t stm32mp1_axi_div[8] = {
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1, 2, 3, 4, 4, 4, 4, 4
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};
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static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = {
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[_HSI] = "HSI",
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[_HSE] = "HSE",
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[_CSI] = "CSI",
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[_LSI] = "LSI",
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[_LSE] = "LSE",
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[_I2S_CKIN] = "I2S_CKIN",
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[_HSI_KER] = "HSI_KER",
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[_HSE_KER] = "HSE_KER",
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[_HSE_KER_DIV2] = "HSE_KER_DIV2",
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[_CSI_KER] = "CSI_KER",
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[_PLL1_P] = "PLL1_P",
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[_PLL1_Q] = "PLL1_Q",
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[_PLL1_R] = "PLL1_R",
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[_PLL2_P] = "PLL2_P",
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[_PLL2_Q] = "PLL2_Q",
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[_PLL2_R] = "PLL2_R",
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[_PLL3_P] = "PLL3_P",
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[_PLL3_Q] = "PLL3_Q",
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[_PLL3_R] = "PLL3_R",
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[_PLL4_P] = "PLL4_P",
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[_PLL4_Q] = "PLL4_Q",
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[_PLL4_R] = "PLL4_R",
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[_ACLK] = "ACLK",
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[_PCLK1] = "PCLK1",
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[_PCLK2] = "PCLK2",
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[_PCLK3] = "PCLK3",
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[_PCLK4] = "PCLK4",
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[_PCLK5] = "PCLK5",
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[_HCLK6] = "KCLK6",
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[_HCLK2] = "HCLK2",
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[_CK_PER] = "CK_PER",
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[_CK_MPU] = "CK_MPU",
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[_CK_MCU] = "CK_MCU",
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[_USB_PHY_48] = "USB_PHY_48",
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};
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/* RCC clock device driver private */
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static unsigned long stm32mp1_osc[NB_OSC];
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static struct spinlock reg_lock;
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@ -2007,6 +2044,165 @@ static void stm32mp1_osc_init(void)
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}
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}
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#ifdef STM32MP_SHARED_RESOURCES
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/*
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* Get the parent ID of the target parent clock, for tagging as secure
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* shared clock dependencies.
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*/
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static int get_parent_id_parent(unsigned int parent_id)
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{
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enum stm32mp1_parent_sel s = _UNKNOWN_SEL;
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enum stm32mp1_pll_id pll_id;
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uint32_t p_sel;
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uintptr_t rcc_base = stm32mp_rcc_base();
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switch (parent_id) {
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case _ACLK:
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case _PCLK4:
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case _PCLK5:
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s = _AXIS_SEL;
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break;
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case _PLL1_P:
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case _PLL1_Q:
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case _PLL1_R:
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pll_id = _PLL1;
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break;
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case _PLL2_P:
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case _PLL2_Q:
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case _PLL2_R:
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pll_id = _PLL2;
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break;
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case _PLL3_P:
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case _PLL3_Q:
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case _PLL3_R:
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pll_id = _PLL3;
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break;
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case _PLL4_P:
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case _PLL4_Q:
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case _PLL4_R:
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pll_id = _PLL4;
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break;
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case _PCLK1:
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case _PCLK2:
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case _HCLK2:
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case _HCLK6:
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case _CK_PER:
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case _CK_MPU:
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case _CK_MCU:
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case _USB_PHY_48:
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/* We do not expect to access these */
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panic();
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break;
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default:
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/* Other parents have no parent */
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return -1;
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}
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if (s != _UNKNOWN_SEL) {
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const struct stm32mp1_clk_sel *sel = clk_sel_ref(s);
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p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) &
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sel->msk;
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if (p_sel < sel->nb_parent) {
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return (int)sel->parent[p_sel];
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}
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} else {
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const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
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p_sel = mmio_read_32(rcc_base + pll->rckxselr) &
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RCC_SELR_REFCLK_SRC_MASK;
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if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) {
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return (int)pll->refclk[p_sel];
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}
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}
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VERBOSE("No parent selected for %s\n",
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stm32mp1_clk_parent_name[parent_id]);
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return -1;
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}
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static void secure_parent_clocks(unsigned long parent_id)
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{
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int grandparent_id;
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switch (parent_id) {
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case _PLL3_P:
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case _PLL3_Q:
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case _PLL3_R:
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stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3);
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break;
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/* These clocks are always secure when RCC is secure */
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case _ACLK:
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case _HCLK2:
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case _HCLK6:
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case _PCLK4:
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case _PCLK5:
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case _PLL1_P:
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case _PLL1_Q:
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case _PLL1_R:
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case _PLL2_P:
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case _PLL2_Q:
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case _PLL2_R:
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case _HSI:
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case _HSI_KER:
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case _LSI:
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case _CSI:
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case _CSI_KER:
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case _HSE:
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case _HSE_KER:
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case _HSE_KER_DIV2:
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case _LSE:
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break;
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default:
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VERBOSE("Cannot secure parent clock %s\n",
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stm32mp1_clk_parent_name[parent_id]);
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panic();
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}
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grandparent_id = get_parent_id_parent(parent_id);
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if (grandparent_id >= 0) {
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secure_parent_clocks(grandparent_id);
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}
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}
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void stm32mp1_register_clock_parents_secure(unsigned long clock_id)
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{
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int parent_id;
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if (!stm32mp1_rcc_is_secure()) {
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return;
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}
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switch (clock_id) {
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case PLL1:
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case PLL2:
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/* PLL1/PLL2 are always secure: nothing to do */
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break;
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case PLL3:
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stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3);
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break;
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case PLL4:
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ERROR("PLL4 cannot be secured\n");
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panic();
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break;
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default:
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/* Others are expected gateable clock */
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parent_id = stm32mp1_clk_get_parent(clock_id);
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if (parent_id < 0) {
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INFO("No parent found for clock %lu\n", clock_id);
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} else {
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secure_parent_clocks(parent_id);
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}
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break;
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}
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}
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#endif /* STM32MP_SHARED_RESOURCES */
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static void sync_earlyboot_clocks_state(void)
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{
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unsigned int idx;
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@ -59,4 +59,7 @@ void stm32mp1_clk_rcc_regs_unlock(void);
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void stm32mp1_stgen_increment(unsigned long long offset_in_ms);
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#ifdef STM32MP_SHARED_RESOURCES
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void stm32mp1_register_clock_parents_secure(unsigned long id);
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#endif
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#endif /* STM32MP1_CLK_H */
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