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drivers: smmu: Fix MISRA defects 

Change-Id: I2954a99d5b72069bcb7bac9d6926c6209d6ba881
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Antonio Nino Diaz 2018-08-21 16:12:29 +01:00
parent 819df3fc09
commit 6d5f0631a6
2 changed files with 17 additions and 13 deletions
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19
drivers/arm/smmu/smmu_v3.c
View File

@ -1,15 +1,12 @@
/* /*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <mmio.h> #include <mmio.h>
#include <smmu_v3.h> #include <smmu_v3.h>
#include <stdbool.h>
/* Test for pending invalidate */
#define INVAL_PENDING(_base) \
smmuv3_read_s_init(_base) & SMMU_S_INIT_INV_ALL_MASK
static inline uint32_t smmuv3_read_s_idr1(uintptr_t base) static inline uint32_t smmuv3_read_s_idr1(uintptr_t base)
{ {
@ -26,6 +23,12 @@ static inline void smmuv3_write_s_init(uintptr_t base, uint32_t value)
mmio_write_32(base + SMMU_S_INIT, value); mmio_write_32(base + SMMU_S_INIT, value);
} }
/* Test for pending invalidate */
static inline bool smmuv3_inval_pending(uintptr_t base)
{
return (smmuv3_read_s_init(base) & SMMU_S_INIT_INV_ALL_MASK) != 0U;
}
/* /*
* Initialize the SMMU by invalidating all secure caches and TLBs. * Initialize the SMMU by invalidating all secure caches and TLBs.
* *
@ -41,14 +44,14 @@ int smmuv3_init(uintptr_t smmu_base)
* SMMU_S_INIT register is accessed. * SMMU_S_INIT register is accessed.
*/ */
idr1_reg = smmuv3_read_s_idr1(smmu_base); idr1_reg = smmuv3_read_s_idr1(smmu_base);
if (!((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) & if (((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) &
SMMU_S_IDR1_SECURE_IMPL_MASK)) { SMMU_S_IDR1_SECURE_IMPL_MASK) == 0U) {
return -1; return -1;
} }
/* Initiate invalidation, and wait for it to finish */ /* Initiate invalidation, and wait for it to finish */
smmuv3_write_s_init(smmu_base, SMMU_S_INIT_INV_ALL_MASK); smmuv3_write_s_init(smmu_base, SMMU_S_INIT_INV_ALL_MASK);
while (INVAL_PENDING(smmu_base)) while (smmuv3_inval_pending(smmu_base))
; ;
return 0; return 0;

11
include/drivers/arm/smmu_v3.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -7,18 +7,19 @@
#ifndef __SMMU_V3_H__ #ifndef __SMMU_V3_H__
#define __SMMU_V3_H__ #define __SMMU_V3_H__
#include <utils_def.h>
#include <stdint.h> #include <stdint.h>
/* SMMUv3 register offsets from device base */ /* SMMUv3 register offsets from device base */
#define SMMU_S_IDR1 0x8004 #define SMMU_S_IDR1 U(0x8004)
#define SMMU_S_INIT 0x803c #define SMMU_S_INIT U(0x803c)
/* SMMU_S_IDR1 register fields */ /* SMMU_S_IDR1 register fields */
#define SMMU_S_IDR1_SECURE_IMPL_SHIFT 31 #define SMMU_S_IDR1_SECURE_IMPL_SHIFT 31
#define SMMU_S_IDR1_SECURE_IMPL_MASK 0x1 #define SMMU_S_IDR1_SECURE_IMPL_MASK U(0x1)
/* SMMU_S_INIT register fields */ /* SMMU_S_INIT register fields */
#define SMMU_S_INIT_INV_ALL_MASK 0x1 #define SMMU_S_INIT_INV_ALL_MASK U(0x1)
int smmuv3_init(uintptr_t smmu_base); int smmuv3_init(uintptr_t smmu_base);