Cortex-A72: Implement workaround for erratum 859971
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
This commit is contained in:
Eleanor Bonnici
Jeenu Viswambharan
parent
45b52c202f
commit
6de9b3364b
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@ -21,6 +21,7 @@ by ARM:
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- `Cortex-A53 MPCore Software Developers Errata Notice`_
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- `Cortex-A57 MPCore Software Developers Errata Notice`_
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- `Cortex-A72 MPCore Software Developers Errata Notice`_
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The errata workarounds are implemented for a particular revision or a set of
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processor revisions. This is checked by the reset handler at runtime. Each
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@ -102,6 +103,12 @@ For Cortex-A57, following errata build flags are defined :
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- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
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For Cortex-A72, following errata build flags are defined :
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- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
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CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
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CPU Specific optimizations
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--------------------------
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@ -137,5 +144,6 @@ architecture that can be enabled by the platform as desired.
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.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/Cortex_A53_MPCore_Software_Developers_Errata_Notice.pdf
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.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf
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.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
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.. _Firmware Design guide: firmware-design.rst
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.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
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@ -34,6 +34,7 @@
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#define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
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#define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
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#define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
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#define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
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/*******************************************************************************
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* L2 Control register specific definitions.
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@ -34,6 +34,7 @@
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#define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
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#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
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#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
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#define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
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/*******************************************************************************
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* L2 Control register specific definitions.
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@ -61,11 +61,46 @@ func cortex_a72_disable_ext_debug
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bx lr
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endfunc cortex_a72_disable_ext_debug
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A72 Errata #859971.
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* This applies only to revision <= r0p3 of Cortex A72.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------
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*/
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func errata_a72_859971_wa
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mov r2,lr
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bl check_errata_859971
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A72_CPUACTLR
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orr64_imm r1, r1, CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH
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stcopr16 r0, r1, CORTEX_A72_CPUACTLR
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1:
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bx lr
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endfunc errata_a72_859971_wa
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func check_errata_859971
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mov r1, #0x03
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b cpu_rev_var_ls
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endfunc check_errata_859971
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A72.
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* -------------------------------------------------
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*/
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func cortex_a72_reset_func
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mov r5, lr
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bl cpu_get_rev_var
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mov r4, r0
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#if ERRATA_A72_859971
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mov r0, r4
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bl errata_a72_859971_wa
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#endif
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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@ -186,6 +221,27 @@ func cortex_a72_cluster_pwr_dwn
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b cortex_a72_disable_ext_debug
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endfunc cortex_a72_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A72. Must follow AAPCS.
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*/
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func cortex_a72_errata_report
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push {r12, lr}
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bl cpu_get_rev_var
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mov r4, r0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A72_859971, cortex_a72, 859971
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pop {r12, lr}
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bx lr
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endfunc cortex_a72_errata_report
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#endif
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declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \
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cortex_a72_reset_func, \
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cortex_a72_core_pwr_dwn, \
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@ -73,20 +73,52 @@ func cortex_a72_disable_ext_debug
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ret
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endfunc cortex_a72_disable_ext_debug
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/* --------------------------------------------------
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* Errata Workaround for Cortex A72 Errata #859971.
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* This applies only to revision <= r0p3 of Cortex A72.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber:
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* --------------------------------------------------
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*/
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func errata_a72_859971_wa
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mov x17,x30
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bl check_errata_859971
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cbz x0, 1f
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mrs x1, CORTEX_A72_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
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msr CORTEX_A72_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a72_859971_wa
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func check_errata_859971
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mov x1, #0x03
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b cpu_rev_var_ls
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endfunc check_errata_859971
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A72.
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* -------------------------------------------------
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*/
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func cortex_a72_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A72_859971
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mov x0, x18
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bl errata_a72_859971_wa
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#endif
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/* ---------------------------------------------
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* As a bare minimum enable the SMP bit.
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* Enable the SMP bit.
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A72_ECTLR_EL1
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orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
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msr CORTEX_A72_ECTLR_EL1, x0
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isb
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ret
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ret x19
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endfunc cortex_a72_reset_func
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/* ----------------------------------------------------
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@ -196,6 +228,27 @@ func cortex_a72_cluster_pwr_dwn
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b cortex_a72_disable_ext_debug
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endfunc cortex_a72_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A72. Must follow AAPCS.
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*/
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func cortex_a72_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A72_859971, cortex_a72, 859971
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a72_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_a72 specific
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* register information for crash reporting.
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@ -95,6 +95,10 @@ ERRATA_A57_833471 ?=0
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# only to revision <= r1p3 of the Cortex A57 cpu.
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ERRATA_A57_859972 ?=0
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# Flag to apply erratum 855971 workaround during reset. This erratum applies
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# only to revision <= r0p3 of the Cortex A72 cpu.
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ERRATA_A72_859971 ?=0
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# Process ERRATA_A53_826319 flag
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$(eval $(call assert_boolean,ERRATA_A53_826319))
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$(eval $(call add_define,ERRATA_A53_826319))
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@ -151,6 +155,10 @@ $(eval $(call add_define,ERRATA_A57_833471))
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$(eval $(call assert_boolean,ERRATA_A57_859972))
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$(eval $(call add_define,ERRATA_A57_859972))
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# Process ERRATA_A72_859971 flag
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$(eval $(call assert_boolean,ERRATA_A72_859971))
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$(eval $(call add_define,ERRATA_A72_859971))
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# Errata build flags
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ifneq (${ERRATA_A53_843419},0)
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TF_LDFLAGS_aarch64 += --fix-cortex-a53-843419
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