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feat(plat/mediatek/mt8186): add RTC drivers 

Add RTC drivers for EOSC calibration.

TEST=build pass
BUG=b:202871018

Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: Ib48c07204c4a614072ba710c042794b59e8a902a
This commit is contained in:
Yuchen Huang 2021-11-12 16:56:33 +08:00 committed by Rex-BC Chen
parent 0fe7ae9c64
commit 6e5d76bac8
3 changed files with 281 additions and 0 deletions
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133
plat/mediatek/mt8186/drivers/rtc/rtc.c Normal file
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@ -0,0 +1,133 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <rtc.h>
static void RTC_Config_Interface(uint32_t addr, uint16_t data,
uint16_t MASK, uint16_t SHIFT)
{
uint16_t pmic_reg = 0;
pmic_reg = RTC_Read(addr);
pmic_reg &= ~(MASK << SHIFT);
pmic_reg |= (data << SHIFT);
RTC_Write(addr, pmic_reg);
}
static void rtc_disable_2sec_reboot(void)
{
uint16_t reboot;
reboot = (RTC_Read(RTC_AL_SEC) & ~RTC_BBPU_2SEC_EN) &
~RTC_BBPU_AUTO_PDN_SEL;
RTC_Write(RTC_AL_SEC, reboot);
RTC_Write_Trigger();
}
static void rtc_xosc_write(uint16_t val, bool reload)
{
uint16_t bbpu;
RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
rtc_busy_wait();
RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
rtc_busy_wait();
RTC_Write(RTC_OSC32CON, val);
rtc_busy_wait();
if (reload) {
bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD;
RTC_Write(RTC_BBPU, bbpu);
RTC_Write_Trigger();
}
}
static void rtc_enable_k_eosc(void)
{
uint16_t osc32;
uint16_t rtc_eosc_cali_td = 8; /* eosc cali period time */
/* Truning on eosc cali mode clock */
RTC_Config_Interface(PMIC_RG_TOP_CON, 1,
PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK,
PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT);
RTC_Config_Interface(PMIC_RG_TOP_CON, 1,
PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK,
PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT);
RTC_Config_Interface(PMIC_RG_SCK_TOP_CKPDN_CON0, 0,
PMIC_RG_RTC_EOSC32_CK_PDN_MASK,
PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT);
switch (rtc_eosc_cali_td) {
case 1:
RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x3,
PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
break;
case 2:
RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x4,
PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
break;
case 4:
RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x5,
PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
break;
case 16:
RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x7,
PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
break;
default:
RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x6,
PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
break;
}
/* Switch the DCXO from 32k-less mode to RTC mode,
* otherwise, EOSC cali will fail
*/
/* RTC mode will have only OFF mode and FPM */
RTC_Config_Interface(PMIC_RG_DCXO_CW02, 0, PMIC_RG_XO_EN32K_MAN_MASK,
PMIC_RG_XO_EN32K_MAN_SHIFT);
RTC_Write(RTC_BBPU,
RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
RTC_Write_Trigger();
/* Enable K EOSC mode for normal power off and then plug out battery */
RTC_Write(RTC_AL_YEA, ((RTC_Read(RTC_AL_YEA) | RTC_K_EOSC_RSV_0)
& (~RTC_K_EOSC_RSV_1)) | RTC_K_EOSC_RSV_2);
RTC_Write_Trigger();
osc32 = RTC_Read(RTC_OSC32CON);
rtc_xosc_write(osc32 | RTC_EMBCK_SRC_SEL, true);
INFO("[RTC] RTC_enable_k_eosc\n");
}
void rtc_power_off_sequence(void)
{
uint16_t bbpu;
rtc_disable_2sec_reboot();
rtc_enable_k_eosc();
/* clear alarm */
bbpu = RTC_BBPU_KEY | RTC_BBPU_CLR | RTC_BBPU_PWREN;
if (Writeif_unlock()) {
RTC_Write(RTC_BBPU, bbpu);
RTC_Write(RTC_AL_MASK, RTC_AL_MASK_DOW);
RTC_Write_Trigger();
mdelay(1);
bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD;
RTC_Write(RTC_BBPU, bbpu);
RTC_Write_Trigger();
INFO("[RTC] BBPU=0x%x, IRQ_EN=0x%x, AL_MSK=0x%x, AL_SEC=0x%x\n",
RTC_Read(RTC_BBPU), RTC_Read(RTC_IRQ_EN),
RTC_Read(RTC_AL_MASK), RTC_Read(RTC_AL_SEC));
}
}

145
plat/mediatek/mt8186/drivers/rtc/rtc.h Normal file
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@ -0,0 +1,145 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef RTC_H
#define RTC_H
#define PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK (1U)
#define PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT (1U)
#define PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK (1U)
#define PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT (3U)
#define PMIC_RG_RTC_EOSC32_CK_PDN_MASK (1U)
#define PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT (2U)
#define PMIC_RG_EOSC_CALI_TD_MASK (7U)
#define PMIC_RG_EOSC_CALI_TD_SHIFT (5U)
#define PMIC_RG_XO_EN32K_MAN_MASK (1U)
#define PMIC_RG_XO_EN32K_MAN_SHIFT (0U)
/* RTC registers */
enum {
RTC_BBPU = 0x0588,
RTC_IRQ_STA = 0x058A,
RTC_IRQ_EN = 0x058C,
RTC_CII_EN = 0x058E
};
enum {
RTC_AL_SEC = 0x05A0,
RTC_AL_MIN = 0x05A2,
RTC_AL_HOU = 0x05A4,
RTC_AL_DOM = 0x05A6,
RTC_AL_DOW = 0x05A8,
RTC_AL_MTH = 0x05AA,
RTC_AL_YEA = 0x05AC,
RTC_AL_MASK = 0x0590
};
enum {
RTC_OSC32CON = 0x05AE,
RTC_CON = 0x05C4,
RTC_WRTGR = 0x05C2
};
enum {
RTC_PDN1 = 0x05B4,
RTC_PDN2 = 0x05B6,
RTC_SPAR0 = 0x05B8,
RTC_SPAR1 = 0x05BA,
RTC_PROT = 0x05BC,
RTC_DIFF = 0x05BE,
RTC_CALI = 0x05C0
};
enum {
RTC_OSC32CON_UNLOCK1 = 0x1A57,
RTC_OSC32CON_UNLOCK2 = 0x2B68
};
enum {
RTC_PROT_UNLOCK1 = 0x586A,
RTC_PROT_UNLOCK2 = 0x9136
};
enum {
RTC_BBPU_PWREN = 1U << 0,
RTC_BBPU_CLR = 1U << 1,
RTC_BBPU_INIT = 1U << 2,
RTC_BBPU_AUTO = 1U << 3,
RTC_BBPU_CLRPKY = 1U << 4,
RTC_BBPU_RELOAD = 1U << 5,
RTC_BBPU_CBUSY = 1U << 6
};
enum {
RTC_AL_MASK_SEC = 1U << 0,
RTC_AL_MASK_MIN = 1U << 1,
RTC_AL_MASK_HOU = 1U << 2,
RTC_AL_MASK_DOM = 1U << 3,
RTC_AL_MASK_DOW = 1U << 4,
RTC_AL_MASK_MTH = 1U << 5,
RTC_AL_MASK_YEA = 1U << 6
};
enum {
RTC_BBPU_AUTO_PDN_SEL = 1U << 6,
RTC_BBPU_2SEC_CK_SEL = 1U << 7,
RTC_BBPU_2SEC_EN = 1U << 8,
RTC_BBPU_2SEC_MODE = 0x3 << 9,
RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11,
RTC_BBPU_2SEC_STAT_STA = 1U << 12
};
enum {
RTC_BBPU_KEY = 0x43 << 8
};
enum {
RTC_EMBCK_SRC_SEL = 1 << 8,
RTC_EMBCK_SEL_MODE = 3 << 6,
RTC_XOSC32_ENB = 1 << 5,
RTC_REG_XOSC32_ENB = 1 << 15
};
enum {
RTC_K_EOSC_RSV_0 = 1 << 8,
RTC_K_EOSC_RSV_1 = 1 << 9,
RTC_K_EOSC_RSV_2 = 1 << 10
};
/* PMIC TOP Register Definition */
enum {
PMIC_RG_TOP_CON = 0x001E,
PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
};
/* PMIC SCK Register Definition */
enum {
PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x051A,
PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x051C,
PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x051E,
PMIC_RG_EOSC_CALI_CON0 = 0x540
};
/* PMIC DCXO Register Definition */
enum {
PMIC_RG_DCXO_CW00 = 0x0788,
PMIC_RG_DCXO_CW02 = 0x0790
};
/* external API */
uint16_t RTC_Read(uint32_t addr);
void RTC_Write(uint32_t addr, uint16_t data);
int32_t rtc_busy_wait(void);
int32_t RTC_Write_Trigger(void);
int32_t Writeif_unlock(void);
void rtc_power_off_sequence(void);
#endif /* RTC_H */

3
plat/mediatek/mt8186/platform.mk
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@ -15,6 +15,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \
-I${MTK_PLAT_SOC}/drivers/pmic/ \
-I${MTK_PLAT_SOC}/drivers/rtc/ \
-I${MTK_PLAT_SOC}/include/
GICV3_SUPPORT_GIC600 := 1
@ -39,6 +40,7 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c \
${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c \
${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \
${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
${MTK_PLAT}/common/mtk_plat_common.c \
${MTK_PLAT}/common/mtk_sip_svc.c \
${MTK_PLAT}/common/params_setup.c \
@ -52,6 +54,7 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_sip_calls.c \
${MTK_PLAT_SOC}/plat_topology.c