Merge changes from topic "mbox-patches" into integration
* changes: intel: common: Clean up mailbox and sip header intel: clear 'PLAT_SEC_ENTRY' in early platform setup
This commit is contained in:
Manish Pandey
TrustedFirmware Code Review
commit
6e97b22456
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -39,6 +39,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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{
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static console_t console;
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mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
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console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
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&console);
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/*
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@ -134,6 +134,8 @@
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#define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16)
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#define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8)
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#define PLAT_SEC_WARM_ENTRY 0
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -9,35 +9,15 @@
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#include <lib/utils_def.h>
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#define MBOX_OFFSET 0xffa30000
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#define MBOX_MAX_JOB_ID 0xf
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#define MBOX_ATF_CLIENT_ID 0x1
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#define MBOX_JOB_ID 0x1
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/* Mailbox interrupt flags and masks */
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#define MBOX_INT_FLAG_COE 0x1
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#define MBOX_INT_FLAG_RIE 0x2
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#define MBOX_INT_FLAG_UAE 0x100
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#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3)
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#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8)))
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/* Mailbox response and status */
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#define MBOX_RESP_BUFFER_SIZE 16
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#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff)
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#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12)
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#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28)
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#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24)
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#define MBOX_STATUS_UA_MASK (1<<8)
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/* Mailbox command and response */
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#define MBOX_CMD_FREE_OFFSET 0x14
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#define MBOX_CMD_BUFFER_SIZE 32
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#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28)
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#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24)
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#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12)
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#define MBOX_INDIRECT (1 << 11)
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#define MBOX_INSUFFICIENT_BUFFER -2
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/* Mailbox Shared Memory Register Map */
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#define MBOX_CIN 0x00
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#define MBOX_ROUT 0x04
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#define MBOX_URG 0x08
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@ -48,60 +28,61 @@
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#define MBOX_CMD_BUFFER 0x40
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#define MBOX_RESP_BUFFER 0xC0
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#define MBOX_RESP_BUFFER_SIZE 16
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#define MBOX_RESP_OK 0
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#define MBOX_RESP_INVALID_CMD 1
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#define MBOX_RESP_UNKNOWN_BR 2
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#define MBOX_RESP_UNKNOWN 3
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#define MBOX_RESP_NOT_CONFIGURED 256
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/* Mailbox SDM doorbell */
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#define MBOX_DOORBELL_TO_SDM 0x400
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#define MBOX_DOORBELL_FROM_SDM 0x480
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/* Mailbox QSPI commands */
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#define MBOX_CMD_RESTART 2
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#define MBOX_CMD_QSPI_OPEN 50
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#define MBOX_CMD_QSPI_CLOSE 51
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#define MBOX_CMD_QSPI_DIRECT 59
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#define MBOX_CMD_GET_IDCODE 16
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#define MBOX_CMD_QSPI_SET_CS 52
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/* Mailbox CANCEL command */
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#define MBOX_CMD_CANCEL 0x3
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/* Mailbox commands */
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/* Mailbox REBOOT commands */
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#define MBOX_CMD_REBOOT_HPS 71
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#define MBOX_CMD_NOOP 0x00
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#define MBOX_CMD_SYNC 0x01
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#define MBOX_CMD_RESTART 0x02
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#define MBOX_CMD_CANCEL 0x03
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#define MBOX_CMD_GET_IDCODE 0x10
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#define MBOX_CMD_REBOOT_HPS 0x47
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/* Mailbox RSU commands */
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#define MBOX_GET_SUBPARTITION_TABLE 90
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#define MBOX_RSU_STATUS 91
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#define MBOX_RSU_UPDATE 92
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/* Reconfiguration Commands */
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#define MBOX_CONFIG_STATUS 0x04
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#define MBOX_RECONFIG 0x06
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#define MBOX_RECONFIG_DATA 0x08
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#define MBOX_RECONFIG_STATUS 0x09
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/* Mailbox RSU macros */
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#define RSU_VERSION_ACMF BIT(8)
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#define RSU_VERSION_ACMF_MASK 0xff00
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/* QSPI Commands */
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#define MBOX_CMD_QSPI_OPEN 0x32
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#define MBOX_CMD_QSPI_CLOSE 0x33
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#define MBOX_CMD_QSPI_SET_CS 0x34
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#define MBOX_CMD_QSPI_DIRECT 0x3B
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/* HPS stage notify command */
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#define MBOX_HPS_STAGE_NOTIFY 93
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/* RSU Commands */
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#define MBOX_GET_SUBPARTITION_TABLE 0x5A
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#define MBOX_RSU_STATUS 0x5B
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#define MBOX_RSU_UPDATE 0x5C
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#define MBOX_HPS_STAGE_NOTIFY 0x5D
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/* Mailbox Definitions */
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#define CMD_DIRECT 0
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#define CMD_CASUAL 0
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#define CMD_URGENT 1
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#define MBOX_RESP_BUFFER_SIZE 16
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#define MBOX_CMD_BUFFER_SIZE 32
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/* Execution states for HPS_STAGE_NOTIFY */
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#define HPS_EXECUTION_STATE_FSBL 0
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#define HPS_EXECUTION_STATE_SSBL 1
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#define HPS_EXECUTION_STATE_OS 2
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/* Mailbox reconfiguration commands */
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#define MBOX_CONFIG_STATUS 4
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#define MBOX_RECONFIG 6
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#define MBOX_RECONFIG_DATA 8
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#define MBOX_RECONFIG_STATUS 9
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/* Generic error handling */
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#define MBOX_TIMEOUT -2047
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/* Status Response */
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#define MBOX_RET_OK 0
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#define MBOX_RET_ERROR -1
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#define MBOX_NO_RESPONSE -2
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#define MBOX_WRONG_ID -3
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#define MBOX_TIMEOUT -2047
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/* Mailbox status */
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/* Reconfig Status Response */
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#define RECONFIG_STATUS_STATE 0
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#define RECONFIG_STATUS_PIN_STATUS 2
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#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
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@ -121,6 +102,36 @@
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#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007
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#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008
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/* Mailbox Macros */
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/* Mailbox interrupt flags and masks */
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#define MBOX_INT_FLAG_COE 0x1
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#define MBOX_INT_FLAG_RIE 0x2
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#define MBOX_INT_FLAG_UAE 0x100
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#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3)
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#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8)))
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/* Mailbox response and status */
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#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff)
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#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12)
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#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28)
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#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24)
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#define MBOX_STATUS_UA_MASK (1<<8)
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/* Mailbox command and response */
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#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28)
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#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24)
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#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12)
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#define MBOX_INDIRECT (1 << 11)
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/* RSU Macros */
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#define RSU_VERSION_ACMF BIT(8)
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#define RSU_VERSION_ACMF_MASK 0xff00
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/* Mailbox Function Definitions */
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void mailbox_set_int(int interrupt_input);
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int mailbox_init(void);
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void mailbox_set_qspi_close(void);
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@ -131,7 +142,6 @@ int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args,
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int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
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int len, int urgent);
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int mailbox_read_response(int job_id, uint32_t *response, int resp_len);
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int mailbox_get_qspi_clock(void);
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void mailbox_reset_cold(void);
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void mailbox_clear_response(void);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -17,21 +17,31 @@
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/* SMC SiP service function identifier */
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/* FPGA Reconfig */
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#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
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#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
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#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
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#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
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#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
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/* Secure Register Access */
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#define INTEL_SIP_SMC_REG_READ 0xC2000007
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#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
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#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009
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/* Remote System Update */
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#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B
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#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
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#define INTEL_SIP_LEGACY_SMC_ECC_DBE 0xC200000D
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#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
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#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
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/* Send Mailbox Command */
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#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E
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/* SiP Definitions */
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -47,6 +47,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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{
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static console_t console;
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mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
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console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
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&console);
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/*
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