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refactor(drivers/marvell/comphy-3700): rename Lane Status 1 register constants 

Rename the Lane Status 1 register constants from LANE_STATUS1 to
LANE_STAT1, to use an abbreviation similar to that for Lane
Configuration registers (where we use LANE_CFGx instead of LANE_CONFIGx
or LANE_CONFIGURATIONx).

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie329d5a93615efe261802a2f027475b602a5c840
This commit is contained in:
Marek Behún 2021-12-08 01:24:36 +01:00
parent 9cf978c6c4
commit 6eb043791e
2 changed files with 5 additions and 5 deletions
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6
drivers/marvell/comphy/phy-comphy-3700.c
View File

@ -782,7 +782,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
udelay(PLL_SET_DELAY_US);
if (comphy_index == COMPHY_LANE2) {
data = COMPHY_LANE_STATUS1 + USB3PHY_LANE2_REG_BASE_OFFSET;
data = COMPHY_LANE_STAT1 + USB3PHY_LANE2_REG_BASE_OFFSET;
mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET,
data);
@ -790,7 +790,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
COMPHY_PLL_TIMEOUT, REG_32BIT);
} else {
ret = polling_with_timeout(LANE_STATUS1_ADDR(USB3) + reg_base,
ret = polling_with_timeout(LANE_STAT1_ADDR(USB3) + reg_base,
TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
COMPHY_PLL_TIMEOUT, REG_16BIT);
}
@ -890,7 +890,7 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
/* Wait for > 55 us to allow PCLK be enabled */
udelay(PLL_SET_DELAY_US);
ret = polling_with_timeout(LANE_STATUS1_ADDR(PCIE) + COMPHY_SD_ADDR,
ret = polling_with_timeout(LANE_STAT1_ADDR(PCIE) + COMPHY_SD_ADDR,
TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
COMPHY_PLL_TIMEOUT, REG_16BIT);
if (ret) {

4
drivers/marvell/comphy/phy-comphy-3700.h
View File

@ -154,8 +154,8 @@ enum {
#define GEN2_TX_DATA_DLY_DEFT (2 << 3)
#define TX_ELEC_IDLE_MODE_EN BIT(0)
#define COMPHY_LANE_STATUS1 0x183
#define LANE_STATUS1_ADDR(unit) (COMPHY_LANE_STATUS1 * PHY_SHFT(unit))
#define COMPHY_LANE_STAT1 0x183
#define LANE_STAT1_ADDR(unit) (COMPHY_LANE_STAT1 * PHY_SHFT(unit))
#define TXDCLK_PCLK_EN BIT(0)
#define COMPHY_LANE_CFG4 0x188