diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst index 725e96b6a..07f258c77 100644 --- a/docs/about/maintainers.rst +++ b/docs/about/maintainers.rst @@ -415,13 +415,13 @@ Arm Reference Design platform ports :|F|: plat/arm/board/rdv1mc/ :|F|: plat/arm/board/sgi575/ -Arm Total Compute(tc0) platform port +Arm Total Compute platform port ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Arunachalam Ganapathy :|G|: `arugan02`_ :|M|: Usama Arif :|G|: `uarif1`_ -:|F|: plat/arm/board/tc0 +:|F|: plat/arm/board/tc HiSilicon HiKey and HiKey960 platform ports ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst index f50dab52e..c834f6ae7 100644 --- a/docs/plat/arm/index.rst +++ b/docs/plat/arm/index.rst @@ -8,7 +8,7 @@ Arm Development Platforms juno/index fvp/index fvp-ve/index - tc0/index + tc/index arm_fpga/index arm-build-options morello/index diff --git a/docs/plat/arm/tc0/index.rst b/docs/plat/arm/tc/index.rst similarity index 73% rename from docs/plat/arm/tc0/index.rst rename to docs/plat/arm/tc/index.rst index 34d1f1342..20d3e562e 100644 --- a/docs/plat/arm/tc0/index.rst +++ b/docs/plat/arm/tc/index.rst @@ -1,7 +1,7 @@ -TC0 Total Compute Platform +TC Total Compute Platform ========================== -Some of the features of TC0 platform referenced in TF-A include: +Some of the features of TC platform referenced in TF-A include: - A `System Control Processor `_ to abstract power and system management tasks away from application @@ -13,6 +13,12 @@ Some of the features of TC0 platform referenced in TF-A include: - SCMI - MHUv2 +Currently, the main difference between TC0 (TARGET_PLATFORM=0) and TC1 +(TARGET_PLATFORM=1) platforms w.r.t to TF-A is the CPUs supported. TC0 has +support for Cortex A510, Cortex A710 and Cortex X2, while TC1 has support for +Cortex A510, Cortex Makalu and Cortex Makalu ELP Arm CPUs. + + Boot Sequence ------------- @@ -34,8 +40,8 @@ Build Procedure (TF-A only) .. code:: shell - make PLAT=tc0 BL33= \ - SCP_BL2= all fip + make PLAT=tc BL33= \ + SCP_BL2= TARGET_PLATFORM={0,1} all fip Enable TBBR by adding the following options to the make command: @@ -47,4 +53,4 @@ Build Procedure (TF-A only) ARM_ROTPK_LOCATION=devel_rsa \ ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem -*Copyright (c) 2020, Arm Limited. All rights reserved.* +*Copyright (c) 2020-2021, Arm Limited. All rights reserved.* diff --git a/fdts/tc0.dts b/fdts/tc.dts similarity index 99% rename from fdts/tc0.dts rename to fdts/tc.dts index 9051b7b7e..f66d55670 100644 --- a/fdts/tc0.dts +++ b/fdts/tc.dts @@ -7,7 +7,7 @@ /dts-v1/; / { - compatible = "arm,tc0"; + compatible = "arm,tc"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; diff --git a/plat/arm/board/tc0/fdts/tc0_fw_config.dts b/plat/arm/board/tc/fdts/tc_fw_config.dts similarity index 100% rename from plat/arm/board/tc0/fdts/tc0_fw_config.dts rename to plat/arm/board/tc/fdts/tc_fw_config.dts diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_manifest.dts similarity index 98% rename from plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts rename to plat/arm/board/tc/fdts/tc_spmc_manifest.dts index 7fb1657b1..a8592f6bf 100644 --- a/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts +++ b/plat/arm/board/tc/fdts/tc_spmc_manifest.dts @@ -110,7 +110,7 @@ }; }; - /* 32MB of TC0_TZC_DRAM1_BASE */ + /* 32MB of TC_TZC_DRAM1_BASE */ memory@fd000000 { device_type = "memory"; reg = <0x0 0xfd000000 0x2000000>; diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts similarity index 98% rename from plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts rename to plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts index 8714d4459..34b4e74c3 100644 --- a/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts +++ b/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts @@ -116,7 +116,7 @@ }; }; - /* 32MB of TC0_TZC_DRAM1_BASE */ + /* 32MB of TC_TZC_DRAM1_BASE */ memory@fd000000 { device_type = "memory"; reg = <0x0 0xfd000000 0x2000000>; diff --git a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts b/plat/arm/board/tc/fdts/tc_tb_fw_config.dts similarity index 100% rename from plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts rename to plat/arm/board/tc/fdts/tc_tb_fw_config.dts diff --git a/plat/arm/board/tc0/include/plat_macros.S b/plat/arm/board/tc/include/plat_macros.S similarity index 100% rename from plat/arm/board/tc0/include/plat_macros.S rename to plat/arm/board/tc/include/plat_macros.S diff --git a/plat/arm/board/tc0/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h similarity index 82% rename from plat/arm/board/tc0/include/platform_def.h rename to plat/arm/board/tc/include/platform_def.h index b169d7720..c8edd2fbb 100644 --- a/plat/arm/board/tc0/include/platform_def.h +++ b/plat/arm/board/tc/include/platform_def.h @@ -29,38 +29,38 @@ * - BL32_BASE when SPD_spmd is enabled * - Region to load Trusted OS */ -#define TC0_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ - TC0_TZC_DRAM1_SIZE) -#define TC0_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */ -#define TC0_TZC_DRAM1_END (TC0_TZC_DRAM1_BASE + \ - TC0_TZC_DRAM1_SIZE - 1) +#define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ + TC_TZC_DRAM1_SIZE) +#define TC_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */ +#define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ + TC_TZC_DRAM1_SIZE - 1) -#define TC0_NS_DRAM1_BASE ARM_DRAM1_BASE -#define TC0_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ +#define TC_NS_DRAM1_BASE ARM_DRAM1_BASE +#define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ ARM_TZC_DRAM1_SIZE - \ - TC0_TZC_DRAM1_SIZE) -#define TC0_NS_DRAM1_END (TC0_NS_DRAM1_BASE + \ - TC0_NS_DRAM1_SIZE - 1) + TC_TZC_DRAM1_SIZE) +#define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + \ + TC_NS_DRAM1_SIZE - 1) /* - * Mappings for TC0 DRAM1 (non-secure) and TC0 TZC DRAM1 (secure) + * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) */ -#define TC0_MAP_NS_DRAM1 MAP_REGION_FLAT( \ - TC0_NS_DRAM1_BASE, \ - TC0_NS_DRAM1_SIZE, \ +#define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + TC_NS_DRAM1_BASE, \ + TC_NS_DRAM1_SIZE, \ MT_MEMORY | MT_RW | MT_NS) -#define TC0_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ - TC0_TZC_DRAM1_BASE, \ - TC0_TZC_DRAM1_SIZE, \ +#define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ + TC_TZC_DRAM1_BASE, \ + TC_TZC_DRAM1_SIZE, \ MT_MEMORY | MT_RW | MT_SECURE) /* - * Max size of SPMC is 2MB for tc0. With SPMD enabled this value corresponds to + * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to * max size of BL32 image. */ #if defined(SPD_spmd) -#define PLAT_ARM_SPMC_BASE TC0_TZC_DRAM1_BASE +#define PLAT_ARM_SPMC_BASE TC_TZC_DRAM1_BASE #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ #endif @@ -152,18 +152,18 @@ #endif -#define TC0_DEVICE_BASE 0x21000000 -#define TC0_DEVICE_SIZE 0x5f000000 +#define TC_DEVICE_BASE 0x21000000 +#define TC_DEVICE_SIZE 0x5f000000 -// TC0_MAP_DEVICE covers different peripherals +// TC_MAP_DEVICE covers different peripherals // available to the platform -#define TC0_MAP_DEVICE MAP_REGION_FLAT( \ - TC0_DEVICE_BASE, \ - TC0_DEVICE_SIZE, \ +#define TC_MAP_DEVICE MAP_REGION_FLAT( \ + TC_DEVICE_BASE, \ + TC_DEVICE_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define TC0_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ +#define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ V2M_FLASH0_SIZE, \ MT_DEVICE | MT_RO | MT_SECURE) @@ -250,14 +250,14 @@ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) /* - * The first region below, TC0_TZC_DRAM1_BASE (0xfd000000) to + * The first region below, TC_TZC_DRAM1_BASE (0xfd000000) to * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 48 MB of DRAM as * secure. The second region gives non secure access to rest of DRAM. */ -#define TC0_TZC_REGIONS_DEF \ - {TC0_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ +#define TC_TZC_REGIONS_DEF \ + {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ - {TC0_NS_DRAM1_BASE, TC0_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ PLAT_ARM_TZC_NS_DEV_ACCESS} /* virtual address used by dynamic mem_protect for chunk_base */ diff --git a/plat/arm/board/tc0/include/tc0_helpers.S b/plat/arm/board/tc/include/tc_helpers.S similarity index 96% rename from plat/arm/board/tc0/include/tc0_helpers.S rename to plat/arm/board/tc/include/tc_helpers.S index 90623a273..5f5485660 100644 --- a/plat/arm/board/tc0/include/tc0_helpers.S +++ b/plat/arm/board/tc/include/tc_helpers.S @@ -15,7 +15,7 @@ /* --------------------------------------------------------------------- * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) * - * Function to calculate the core position on TC0. + * Function to calculate the core position on TC. * * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) + * (CPUId * PLAT_MAX_PE_PER_CPU) + diff --git a/plat/arm/board/tc/include/tc_plat.h b/plat/arm/board/tc/include/tc_plat.h new file mode 100644 index 000000000..28c0308e6 --- /dev/null +++ b/plat/arm/board/tc/include/tc_plat.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TC_PLAT_H +#define TC_PLAT_H + +void tc_bl31_common_platform_setup(void); + +#endif /* TC_PLAT_H */ diff --git a/plat/arm/board/tc0/platform.mk b/plat/arm/board/tc/platform.mk similarity index 57% rename from plat/arm/board/tc0/platform.mk rename to plat/arm/board/tc/platform.mk index 5ae87d177..8db764ca1 100644 --- a/plat/arm/board/tc0/platform.mk +++ b/plat/arm/board/tc/platform.mk @@ -1,8 +1,12 @@ -# Copyright (c) 2020-2021, Arm Limited. All rights reserved. +# Copyright (c) 2021, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # +ifeq ($(filter ${TARGET_PLATFORM}, 0 1),) + $(error TARGET_PLATFORM must be 0 or 1) +endif + CSS_LOAD_SCP_IMAGES := 1 CSS_USE_SCMI_SDS_DRIVER := 1 @@ -39,46 +43,57 @@ override NEED_BL2U := no override ARM_PLAT_MT := 1 -TC0_BASE = plat/arm/board/tc0 +TC_BASE = plat/arm/board/tc -PLAT_INCLUDES += -I${TC0_BASE}/include/ +PLAT_INCLUDES += -I${TC_BASE}/include/ -TC0_CPU_SOURCES := lib/cpus/aarch64/cortex_a510.S \ - lib/cpus/aarch64/cortex_a710.S \ +# Common CPU libraries +TC_CPU_SOURCES := lib/cpus/aarch64/cortex_a510.S + +# CPU libraries for TARGET_PLATFORM=0 +ifeq (${TARGET_PLATFORM}, 0) +TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a710.S \ lib/cpus/aarch64/cortex_x2.S +endif -INTERCONNECT_SOURCES := ${TC0_BASE}/tc0_interconnect.c +# CPU libraries for TARGET_PLATFORM=1 +ifeq (${TARGET_PLATFORM}, 1) +TC_CPU_SOURCES += lib/cpus/aarch64/cortex_makalu.S \ + lib/cpus/aarch64/cortex_makalu_elp_arm.S +endif -PLAT_BL_COMMON_SOURCES += ${TC0_BASE}/tc0_plat.c \ - ${TC0_BASE}/include/tc0_helpers.S +INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c + +PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_plat.c \ + ${TC_BASE}/include/tc_helpers.S BL1_SOURCES += ${INTERCONNECT_SOURCES} \ - ${TC0_CPU_SOURCES} \ - ${TC0_BASE}/tc0_trusted_boot.c \ - ${TC0_BASE}/tc0_err.c \ + ${TC_CPU_SOURCES} \ + ${TC_BASE}/tc_trusted_boot.c \ + ${TC_BASE}/tc_err.c \ drivers/arm/sbsa/sbsa.c -BL2_SOURCES += ${TC0_BASE}/tc0_security.c \ - ${TC0_BASE}/tc0_err.c \ - ${TC0_BASE}/tc0_trusted_boot.c \ +BL2_SOURCES += ${TC_BASE}/tc_security.c \ + ${TC_BASE}/tc_err.c \ + ${TC_BASE}/tc_trusted_boot.c \ lib/utils/mem_region.c \ drivers/arm/tzc/tzc400.c \ plat/arm/common/arm_tzc400.c \ plat/arm/common/arm_nor_psci_mem_protect.c BL31_SOURCES += ${INTERCONNECT_SOURCES} \ - ${TC0_CPU_SOURCES} \ + ${TC_CPU_SOURCES} \ ${ENT_GIC_SOURCES} \ - ${TC0_BASE}/tc0_bl31_setup.c \ - ${TC0_BASE}/tc0_topology.c \ + ${TC_BASE}/tc_bl31_setup.c \ + ${TC_BASE}/tc_topology.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c # Add the FDT_SOURCES and options for Dynamic Config -FDT_SOURCES += ${TC0_BASE}/fdts/${PLAT}_fw_config.dts \ - ${TC0_BASE}/fdts/${PLAT}_tb_fw_config.dts +FDT_SOURCES += ${TC_BASE}/fdts/${PLAT}_fw_config.dts \ + ${TC_BASE}/fdts/${PLAT}_tb_fw_config.dts FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb @@ -89,24 +104,24 @@ $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) ifeq (${SPD},spmd) ifeq ($(ARM_SPMC_MANIFEST_DTS),) -ARM_SPMC_MANIFEST_DTS := ${TC0_BASE}/fdts/${PLAT}_spmc_manifest.dts +ARM_SPMC_MANIFEST_DTS := ${TC_BASE}/fdts/${PLAT}_spmc_manifest.dts endif FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} -TC0_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb +TC_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb # Add the TOS_FW_CONFIG to FIP and specify the same to certtool -$(eval $(call TOOL_ADD_PAYLOAD,${TC0_TOS_FW_CONFIG},--tos-fw-config,${TC0_TOS_FW_CONFIG})) +$(eval $(call TOOL_ADD_PAYLOAD,${TC_TOS_FW_CONFIG},--tos-fw-config,${TC_TOS_FW_CONFIG})) endif #Device tree -TC0_HW_CONFIG_DTS := fdts/tc0.dts -TC0_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb -FDT_SOURCES += ${TC0_HW_CONFIG_DTS} -$(eval TC0_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC0_HW_CONFIG_DTS))) +TC_HW_CONFIG_DTS := fdts/tc.dts +TC_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb +FDT_SOURCES += ${TC_HW_CONFIG_DTS} +$(eval TC_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC_HW_CONFIG_DTS))) # Add the HW_CONFIG to FIP and specify the same to certtool -$(eval $(call TOOL_ADD_PAYLOAD,${TC0_HW_CONFIG},--hw-config,${TC0_HW_CONFIG})) +$(eval $(call TOOL_ADD_PAYLOAD,${TC_HW_CONFIG},--hw-config,${TC_HW_CONFIG})) override CTX_INCLUDE_AARCH32_REGS := 0 diff --git a/plat/arm/board/tc0/tc0_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c similarity index 83% rename from plat/arm/board/tc0/tc0_bl31_setup.c rename to plat/arm/board/tc/tc_bl31_setup.c index b91b11c9d..ecec26c05 100644 --- a/plat/arm/board/tc0/tc0_bl31_setup.c +++ b/plat/arm/board/tc/tc_bl31_setup.c @@ -7,7 +7,7 @@ #include #include -#include +#include #include #include @@ -16,7 +16,7 @@ #include #include -static scmi_channel_plat_info_t tc0_scmi_plat_info[] = { +static scmi_channel_plat_info_t tc_scmi_plat_info[] = { { .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0), @@ -28,13 +28,13 @@ static scmi_channel_plat_info_t tc0_scmi_plat_info[] = { void bl31_platform_setup(void) { - tc0_bl31_common_platform_setup(); + tc_bl31_common_platform_setup(); } scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id) { - return &tc0_scmi_plat_info[channel_id]; + return &tc_scmi_plat_info[channel_id]; } @@ -44,7 +44,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); } -void tc0_bl31_common_platform_setup(void) +void tc_bl31_common_platform_setup(void) { arm_bl31_platform_setup(); } diff --git a/plat/arm/board/tc0/tc0_err.c b/plat/arm/board/tc/tc_err.c similarity index 92% rename from plat/arm/board/tc0/tc0_err.c rename to plat/arm/board/tc/tc_err.c index 83f2e9f6a..9ed7e9299 100644 --- a/plat/arm/board/tc0/tc0_err.c +++ b/plat/arm/board/tc/tc_err.c @@ -7,7 +7,7 @@ #include /* - * tc0 error handler + * tc error handler */ void __dead2 plat_arm_error_handler(int err) { diff --git a/plat/arm/board/tc0/tc0_interconnect.c b/plat/arm/board/tc/tc_interconnect.c similarity index 100% rename from plat/arm/board/tc0/tc0_interconnect.c rename to plat/arm/board/tc/tc_interconnect.c diff --git a/plat/arm/board/tc0/tc0_plat.c b/plat/arm/board/tc/tc_plat.c similarity index 96% rename from plat/arm/board/tc0/tc0_plat.c rename to plat/arm/board/tc/tc_plat.c index b5698c098..3863a0a13 100644 --- a/plat/arm/board/tc0/tc0_plat.c +++ b/plat/arm/board/tc/tc_plat.c @@ -28,19 +28,19 @@ #if IMAGE_BL1 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, - TC0_FLASH0_RO, - TC0_MAP_DEVICE, + TC_FLASH0_RO, + TC_MAP_DEVICE, {0} }; #endif #if IMAGE_BL2 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, - TC0_FLASH0_RO, - TC0_MAP_DEVICE, - TC0_MAP_NS_DRAM1, + TC_FLASH0_RO, + TC_MAP_DEVICE, + TC_MAP_NS_DRAM1, #if defined(SPD_spmd) - TC0_MAP_TZC_DRAM1, + TC_MAP_TZC_DRAM1, #endif #if ARM_BL31_IN_DRAM ARM_MAP_BL31_SEC_DRAM, @@ -62,7 +62,7 @@ const mmap_region_t plat_arm_mmap[] = { const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, V2M_MAP_IOFPGA, - TC0_MAP_DEVICE, + TC_MAP_DEVICE, #if SPM_MM ARM_SPM_BUF_EL3_MMAP, #endif diff --git a/plat/arm/board/tc0/tc0_security.c b/plat/arm/board/tc/tc_security.c similarity index 95% rename from plat/arm/board/tc0/tc0_security.c rename to plat/arm/board/tc/tc_security.c index f54376203..6a345010a 100644 --- a/plat/arm/board/tc0/tc0_security.c +++ b/plat/arm/board/tc/tc_security.c @@ -8,7 +8,7 @@ #include static const arm_tzc_regions_info_t tzc_regions[] = { - TC0_TZC_REGIONS_DEF, + TC_TZC_REGIONS_DEF, {} }; diff --git a/plat/arm/board/tc0/tc0_topology.c b/plat/arm/board/tc/tc_topology.c similarity index 96% rename from plat/arm/board/tc0/tc0_topology.c rename to plat/arm/board/tc/tc_topology.c index 8cfc3b50e..9e18da6de 100644 --- a/plat/arm/board/tc0/tc0_topology.c +++ b/plat/arm/board/tc/tc_topology.c @@ -10,7 +10,7 @@ /****************************************************************************** * The power domain tree descriptor. ******************************************************************************/ -const unsigned char tc0_pd_tree_desc[] = { +const unsigned char tc_pd_tree_desc[] = { PLAT_ARM_CLUSTER_COUNT, PLAT_MAX_CPUS_PER_CLUSTER, }; @@ -20,7 +20,7 @@ const unsigned char tc0_pd_tree_desc[] = { ******************************************************************************/ const unsigned char *plat_get_power_domain_tree_desc(void) { - return tc0_pd_tree_desc; + return tc_pd_tree_desc; } /******************************************************************************* diff --git a/plat/arm/board/tc0/tc0_trusted_boot.c b/plat/arm/board/tc/tc_trusted_boot.c similarity index 100% rename from plat/arm/board/tc0/tc0_trusted_boot.c rename to plat/arm/board/tc/tc_trusted_boot.c diff --git a/plat/arm/board/tc0/include/tc0_plat.h b/plat/arm/board/tc0/include/tc0_plat.h deleted file mode 100644 index f0cb43132..000000000 --- a/plat/arm/board/tc0/include/tc0_plat.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef tc0_bl31_common_platform_setup_PLAT_H -#define tc0_bl31_common_platform_setup_PLAT_H - -void tc0_bl31_common_platform_setup(void); - -#endif /* tc0_bl31_common_platform_setup_PLAT_H */