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Merge pull request #1777 from glneo/runtime-gicr 

ti: k3: common: Add support for runtime detection of GICR base address
This commit is contained in:
Antonio Niño Díaz 2019-01-25 09:21:42 +00:00 committed by GitHub
parent 2501a03797 b5443284f4
commit 6eee5864f8
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 26 additions and 9 deletions
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1
include/drivers/arm/gicv3.h
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@ -84,6 +84,7 @@
#define GICR_PCPUBASE_SHIFT 0x11
#define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */
#define GICR_CTLR U(0x0)
#define GICR_IIDR U(0x04)
#define GICR_TYPER U(0x08)
#define GICR_WAKER U(0x14)
#define GICR_PROPBASER U(0x70)

5
plat/ti/k3/common/k3_bl31_setup.c
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@ -23,8 +23,7 @@
const mmap_region_t plat_k3_mmap[] = {
MAP_REGION_FLAT(SHARED_RAM_BASE, SHARED_RAM_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(K3_USART_BASE_ADDRESS, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(K3_GICD_BASE, K3_GICD_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(K3_GICR_BASE, K3_GICR_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SEC_PROXY_DATA_BASE, SEC_PROXY_DATA_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
@ -116,7 +115,7 @@ void bl31_plat_arch_setup(void)
void bl31_platform_setup(void)
{
k3_gic_driver_init(K3_GICD_BASE, K3_GICR_BASE);
k3_gic_driver_init(K3_GIC_BASE);
k3_gic_init();
ti_sci_init();

21
plat/ti/k3/common/k3_gicv3.c
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@ -6,10 +6,12 @@
#include <platform_def.h>
#include <assert.h>
#include <common/bl_common.h>
#include <common/interrupt_props.h>
#include <drivers/arm/gicv3.h>
#include <lib/utils.h>
#include <lib/mmio.h>
#include <plat/common/platform.h>
#include <k3_gicv3.h>
@ -35,8 +37,25 @@ gicv3_driver_data_t k3_gic_data = {
.mpidr_to_core_pos = k3_mpidr_to_core_pos,
};
void k3_gic_driver_init(uintptr_t gicd_base, uintptr_t gicr_base)
void k3_gic_driver_init(uintptr_t gic_base)
{
/* GIC Distributor is always at the base of the IP */
uintptr_t gicd_base = gic_base;
/* GIC Redistributor base is run-time detected */
uintptr_t gicr_base = 0;
for (unsigned int gicr_shift = 18; gicr_shift < 21; gicr_shift++) {
uintptr_t gicr_check = gic_base + BIT(gicr_shift);
uint32_t iidr = mmio_read_32(gicr_check + GICR_IIDR);
if (iidr != 0) {
/* Found the GICR base */
gicr_base = gicr_check;
break;
}
}
/* Assert if we have not found the GICR base */
assert(gicr_base != 0);
/*
* The GICv3 driver is initialized in EL3 and does not need
* to be initialized again in SEL1. This is because the S-EL1

2
plat/ti/k3/include/k3_gicv3.h
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@ -9,7 +9,7 @@
#include <stdint.h>
void k3_gic_driver_init(uintptr_t gicd_base, uintptr_t gicr_base);
void k3_gic_driver_init(uintptr_t gic_base);
void k3_gic_init(void);
void k3_gic_cpuif_enable(void);
void k3_gic_cpuif_disable(void);

6
plat/ti/k3/include/platform_def.h
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@ -185,10 +185,8 @@
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE)
#define K3_GICD_BASE 0x01800000
#define K3_GICD_SIZE 0x10000
#define K3_GICR_BASE 0x01880000
#define K3_GICR_SIZE 0x100000
#define K3_GIC_BASE 0x01800000
#define K3_GIC_SIZE 0x200000
#define SEC_PROXY_DATA_BASE 0x32C00000
#define SEC_PROXY_DATA_SIZE 0x80000