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Merge "n1sdp: fix DMC ECC enablement sequence in N1SDP platform" into integration

This commit is contained in:
Soby Mathew 2019-07-23 15:18:58 +00:00 committed by TrustedFirmware Code Review
parent 4dc74ca387 7428bbf443
commit 6ef6157e76
2 changed files with 17 additions and 0 deletions
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9
plat/arm/board/n1sdp/n1sdp_bl31_setup.c
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@ -80,8 +80,17 @@ void dmc_ecc_setup(uint32_t ddr_size_gb)
flush_dcache_range(ARM_DRAM2_BASE, dram2_size);
INFO("Enabling ECC on DMCs\n");
/* Set DMCs to CONFIG state before writing ERR0CTLR0 register */
mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
/* Enable ECC in DMCs */
mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
/* Set DMCs to READY state */
mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
}
void copy_bl33(uint32_t src, uint32_t dst, uint32_t size)

8
plat/arm/board/n1sdp/n1sdp_def.h
View File

@ -25,10 +25,18 @@
#define N1SDP_SDS_BL33_INFO_OFFSET 0
#define N1SDP_SDS_BL33_INFO_SIZE 12
/* DMC memory command registers */
#define N1SDP_DMC0_MEMC_CMD_REG 0x4E000008
#define N1SDP_DMC1_MEMC_CMD_REG 0x4E100008
/* DMC ERR0CTLR0 registers */
#define N1SDP_DMC0_ERR0CTLR0_REG 0x4E000708
#define N1SDP_DMC1_ERR0CTLR0_REG 0x4E100708
/* DMC memory commands */
#define N1SDP_DMC_MEMC_CMD_CONFIG 0
#define N1SDP_DMC_MEMC_CMD_READY 3
/* DMC ECC enable bit in ERR0CTLR0 register */
#define N1SDP_DMC_ERR0CTLR0_ECC_EN 0x1