From 6f512a3dfd61662dbdae4912fb6a320ae4d754d5 Mon Sep 17 00:00:00 2001 From: Dimitris Papastamos Date: Tue, 20 Jun 2017 09:25:10 +0100 Subject: [PATCH] aarch32: Apply workaround for errata 813419 of Cortex-A57 TLBI instructions for monitor mode won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI twice each time. Even though this errata is only needed in r0p0, the current errata framework is not prepared to apply run-time workarounds. The current one is always applied if compiled in, regardless of the CPU or its revision. The `DSB` instruction used when initializing the translation tables has been changed to `DSB ISH` as an optimization and to be consistent with the barriers used for the workaround. NOTE: This workaround is present in AArch64 TF and already enabled by default on Juno. Change-Id: I10b0baa304ed64b13b7b26ea766e61461e759dfa Signed-off-by: Dimitris Papastamos --- include/lib/aarch32/arch_helpers.h | 27 +++++++++++++++++-- lib/xlat_tables/aarch32/xlat_tables.c | 2 +- lib/xlat_tables_v2/aarch32/xlat_tables_arch.c | 2 +- 3 files changed, 27 insertions(+), 4 deletions(-) diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h index e652a59ec..bd1ac25e4 100644 --- a/include/lib/aarch32/arch_helpers.h +++ b/include/lib/aarch32/arch_helpers.h @@ -100,15 +100,30 @@ static inline void write_ ## _name(const u_register_t v) \ * Macros to create inline functions for tlbi operations *********************************************************************/ +#if ERRATA_A57_813419 +/* + * Define function for TLBI instruction with type specifier that + * implements the workaround for errata 813419 of Cortex-A57 + */ #define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ static inline void tlbi##_op(void) \ { \ u_register_t v = 0; \ __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ + __asm__ volatile ("dsb ish");\ + __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ } -#define _DEFINE_BPIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ -static inline void bpi##_op(void) \ +#define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ +static inline void tlbi##_op(u_register_t v) \ +{ \ + __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ + __asm__ volatile ("dsb ish");\ + __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ +} +#else +#define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ +static inline void tlbi##_op(void) \ { \ u_register_t v = 0; \ __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ @@ -119,6 +134,14 @@ static inline void tlbi##_op(u_register_t v) \ { \ __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ } +#endif /* ERRATA_A57_813419 */ + +#define _DEFINE_BPIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ +static inline void bpi##_op(void) \ +{ \ + u_register_t v = 0; \ + __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ +} /* Define function for simple TLBI operation */ #define DEFINE_TLBIOP_FUNC(_op, ...) \ diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c index 3c9051c34..9c1562407 100644 --- a/lib/xlat_tables/aarch32/xlat_tables.c +++ b/lib/xlat_tables/aarch32/xlat_tables.c @@ -149,7 +149,7 @@ void enable_mmu_secure(unsigned int flags) * and translation register writes are committed * before enabling the MMU */ - dsb(); + dsbish(); isb(); sctlr = read_sctlr(); diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c index afc65e7d0..40fd2d0b0 100644 --- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c @@ -141,7 +141,7 @@ void enable_mmu_internal_secure(unsigned int flags, uint64_t *base_table) * and translation register writes are committed * before enabling the MMU */ - dsb(); + dsbish(); isb(); sctlr = read_sctlr();