FVP: map non-secure DRAM1 in the MMU
This patch maps the non-secure region of DRAM1 in the MMU. The non-secure region comprises the whole DRAM1 (0x80000000 - 0xffffffff) excluding the top 16 MB (0xff000000 - 0xffffffff). The TrustZone controller configures this 16 MB region as secure memory, so it can not be accessed in non-secure mode. The number of MMU tables in BL2 has been increased to 3 because the new size of the non-secure region in DRAM requires an extra L2 table. Change-Id: I5ad080c6e181f6b6060e15cebb1d18b7fa128cf5
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@ -66,8 +66,8 @@ plat_config_t plat_config;
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DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_DRAM1 MAP_REGION_FLAT(DRAM1_BASE, \
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DRAM1_SIZE, \
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#define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
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DRAM1_NS_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_TSP_SEC_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
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@ -94,7 +94,7 @@ const mmap_region_t fvp_mmap[] = {
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MAP_FLASH0,
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MAP_DEVICE0,
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MAP_DEVICE1,
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MAP_DRAM1,
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MAP_DRAM1_NS,
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MAP_TSP_SEC_MEM,
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{0}
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};
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@ -278,8 +278,8 @@ void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
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******************************************************************************/
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void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
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{
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bl33_meminfo->total_base = DRAM_BASE;
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bl33_meminfo->total_size = DRAM_SIZE - DRAM1_SEC_SIZE;
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bl33_meminfo->free_base = DRAM_BASE;
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bl33_meminfo->free_size = DRAM_SIZE - DRAM1_SEC_SIZE;
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bl33_meminfo->total_base = DRAM1_NS_BASE;
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bl33_meminfo->total_size = DRAM1_NS_SIZE;
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bl33_meminfo->free_base = DRAM1_NS_BASE;
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bl33_meminfo->free_size = DRAM1_NS_SIZE;
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}
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@ -82,7 +82,15 @@
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#define DRAM1_BASE 0x80000000ull
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#define DRAM1_SIZE 0x80000000ull
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#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1)
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/* Define the top 16 MB of DRAM1 as secure */
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#define DRAM1_SEC_SIZE 0x01000000ull
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#define DRAM1_SEC_BASE (DRAM1_BASE + DRAM1_SIZE - DRAM1_SEC_SIZE)
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#define DRAM1_SEC_END (DRAM1_SEC_BASE + DRAM1_SEC_SIZE - 1)
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#define DRAM1_NS_BASE DRAM1_BASE
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#define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_SEC_SIZE)
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#define DRAM1_NS_END (DRAM1_NS_BASE + DRAM1_NS_SIZE - 1)
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#define DRAM_BASE DRAM1_BASE
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#define DRAM_SIZE DRAM1_SIZE
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@ -89,16 +89,17 @@ void fvp_security_setup(void)
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* Allow only non-secure access to all DRAM to supported devices.
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* Give access to the CPUs and Virtio. Some devices
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* would normally use the default ID so allow that too. We use
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* two regions to cover the blocks of physical memory in the FVPs.
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* two regions to cover the blocks of physical memory in the FVPs
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* plus one region to reserve some memory as secure.
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*
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* Software executing in the secure state, such as a secure
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* boot-loader, can access the DRAM by using the NS attributes in
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* the MMU translation tables and descriptors.
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*/
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/* Set to cover the first block of DRAM */
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/* Region 1 set to cover the Non-Secure DRAM */
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tzc_configure_region(FILTER_SHIFT(0), 1,
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DRAM1_BASE, DRAM1_END - DRAM1_SEC_SIZE,
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DRAM1_NS_BASE, DRAM1_NS_END,
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TZC_REGION_S_NONE,
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) |
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) |
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@ -106,14 +107,14 @@ void fvp_security_setup(void)
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) |
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD));
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/* Set to cover the secure reserved region */
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tzc_configure_region(FILTER_SHIFT(0), 3,
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(DRAM1_END - DRAM1_SEC_SIZE) + 1 , DRAM1_END,
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/* Region 2 set to cover the Secure DRAM */
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tzc_configure_region(FILTER_SHIFT(0), 2,
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DRAM1_SEC_BASE, DRAM1_SEC_END,
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TZC_REGION_S_RDWR,
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0x0);
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/* Set to cover the second block of DRAM */
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tzc_configure_region(FILTER_SHIFT(0), 2,
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/* Region 3 set to cover the second block of DRAM */
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tzc_configure_region(FILTER_SHIFT(0), 3,
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DRAM2_BASE, DRAM2_END, TZC_REGION_S_NONE,
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) |
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) |
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@ -154,7 +154,11 @@
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES 2
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#if IMAGE_BL2
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# define MAX_XLAT_TABLES 3
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#else
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# define MAX_XLAT_TABLES 2
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#endif
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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