plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board
Add support for the iEi Puzzle-M801 board that is based on the Marvell Armada 88F8040 SoC. It supports 1 x 288-pin DIMM, DDR4 2400MHz up to 16 GB (ECC). The iEi Puzzle-M801 board is using a custom MCU to handle board power management. The MCU is managing the boards power LEDs, fans and some other periferals. It's using UART for communication. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: I0826ef8bf651b69aad5803184f20930ac7212ef8
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148798cd15
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/mentor/mi2cv.h>
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#include <lib/mmio.h>
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#include <mv_ddr_if.h>
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#include <mvebu_def.h>
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#include <plat_marvell.h>
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#define MVEBU_AP_MPP_CTRL0_7_REG MVEBU_AP_MPP_REGS(0)
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#define MVEBU_AP_MPP_CTRL4_OFFS 16
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#define MVEBU_AP_MPP_CTRL5_OFFS 20
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#define MVEBU_AP_MPP_CTRL4_I2C0_SDA_ENA 0x3
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#define MVEBU_AP_MPP_CTRL5_I2C0_SCK_ENA 0x3
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#define MVEBU_CP_MPP_CTRL37_OFFS 20
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#define MVEBU_CP_MPP_CTRL38_OFFS 24
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#define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA 0x2
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#define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA 0x2
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#define MVEBU_MPP_CTRL_MASK 0xf
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/*
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* This struct provides the DRAM training code with
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* the appropriate board DRAM configuration
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*/
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static struct mv_ddr_topology_map board_topology_map = {
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/* Board with 1CS 8Gb x4 devices of Micron 2400T */
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
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{ { { {0x1, 0x0, 0, 0}, /* FIXME: change the cs mask for all 64 bit */
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0} },
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/* TODO: double check if the speed bin is 2400T */
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SPEED_BIN_DDR_2400T, /* speed_bin */
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MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
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MV_DDR_DIE_CAP_8GBIT, /* die capacity */
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MV_DDR_FREQ_SAR, /* frequency */
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0, 0, /* cas_l, cas_wl */
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MV_DDR_TEMP_LOW} }, /* temperature */
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MV_DDR_64BIT_BUS_MASK, /* subphys mask */
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MV_DDR_CFG_SPD, /* ddr configuration data source */
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{ {0} }, /* raw spd data */
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{0}, /* timing parameters */
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{ /* electrical configuration */
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{ /* memory electrical configuration */
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MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
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{
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MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
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},
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{
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MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
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MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
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},
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MV_DDR_DIC_RZQ_DIV7 /* dic */
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},
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{ /* phy electrical configuration */
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MV_DDR_OHM_30, /* data_drv_p */
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MV_DDR_OHM_30, /* data_drv_n */
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MV_DDR_OHM_30, /* ctrl_drv_p */
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MV_DDR_OHM_30, /* ctrl_drv_n */
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{
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MV_DDR_OHM_60, /* odt_p 1cs */
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MV_DDR_OHM_120 /* odt_p 2cs */
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},
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{
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MV_DDR_OHM_60, /* odt_n 1cs */
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MV_DDR_OHM_120 /* odt_n 2cs */
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},
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},
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{ /* mac electrical configuration */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
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MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
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},
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}
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};
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
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{
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/* Return the board topology as defined in the board code */
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return &board_topology_map;
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}
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static void mpp_config(void)
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{
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uint32_t val;
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uintptr_t reg;
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/* configure ap mmps 4, 5 to I2C */
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reg = MVEBU_AP_MPP_CTRL0_7_REG;
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val = mmio_read_32(reg);
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val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_AP_MPP_CTRL4_OFFS) |
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(MVEBU_MPP_CTRL_MASK << MVEBU_AP_MPP_CTRL5_OFFS));
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val |= ((MVEBU_AP_MPP_CTRL4_I2C0_SDA_ENA << MVEBU_AP_MPP_CTRL4_OFFS) |
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(MVEBU_AP_MPP_CTRL5_I2C0_SCK_ENA << MVEBU_AP_MPP_CTRL5_OFFS));
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mmio_write_32(reg, val);
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}
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/*
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* This function may modify the default DRAM parameters
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* based on information received from SPD or bootloader
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* configuration located on non volatile storage
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*/
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void plat_marvell_dram_update_topology(void)
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{
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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INFO("Gathering DRAM information\n");
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if (tm->cfg_src == MV_DDR_CFG_SPD) {
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/* configure MPPs to enable i2c */
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mpp_config();
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/* initialize the MVEBU_AP_I2C_BASE I2C bus */
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i2c_init((void *)MVEBU_AP_I2C_BASE);
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/* select SPD memory page 0 to access DRAM configuration */
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i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1);
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/* read data from spd */
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i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
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sizeof(tm->spd_data.all_bytes));
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}
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}
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <armada_common.h>
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/*
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* If bootrom is currently at BLE there's no need to include the memory
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* maps structure at this point
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*/
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#include <mvebu_def.h>
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* GPIO Configuration
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*****************************************************************************
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*/
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#define MPP_CONTROL_REGISTER 0xf2440018
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#define MPP_CONTROL_MPP_SEL_52_MASK 0xf0000
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#define GPIO_DATA_OUT1_REGISTER 0xf2440140
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#define GPIO_DATA_OUT_EN_CTRL1_REGISTER 0xf2440144
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#define GPIO52_MASK 0x100000
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/* Reset PCIe via GPIO number 52 */
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int marvell_gpio_config(void)
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{
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uint32_t reg;
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reg = mmio_read_32(MPP_CONTROL_REGISTER);
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reg |= MPP_CONTROL_MPP_SEL_52_MASK;
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mmio_write_32(MPP_CONTROL_REGISTER, reg);
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reg = mmio_read_32(GPIO_DATA_OUT1_REGISTER);
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reg |= GPIO52_MASK;
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mmio_write_32(GPIO_DATA_OUT1_REGISTER, reg);
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reg = mmio_read_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER);
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reg &= ~GPIO52_MASK;
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mmio_write_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER, reg);
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udelay(100);
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return 0;
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}
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/*****************************************************************************
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* AMB Configuration
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*****************************************************************************
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*/
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struct addr_map_win amb_memory_map[] = {
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/* CP1 SPI1 CS0 Direct Mode access */
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{0xf900, 0x1000000, AMB_SPI1_CS0_ID},
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};
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int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
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uintptr_t base)
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{
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*win = amb_memory_map;
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if (*win == NULL)
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*size = 0;
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else
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*size = ARRAY_SIZE(amb_memory_map);
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return 0;
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}
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#endif
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/*****************************************************************************
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* IO WIN Configuration
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*****************************************************************************
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*/
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struct addr_map_win io_win_memory_map[] = {
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/* CP1 (MCI0) internal regs */
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{0x00000000f4000000, 0x2000000, MCI_0_TID},
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#ifndef IMAGE_BLE
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/* PCIe0 and SPI1_CS0 (RUNIT) on CP1*/
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{0x00000000f9000000, 0x2000000, MCI_0_TID},
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/* PCIe1 on CP1*/
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{0x00000000fb000000, 0x1000000, MCI_0_TID},
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/* PCIe2 on CP1*/
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{0x00000000fc000000, 0x1000000, MCI_0_TID},
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/* MCI 0 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
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/* MCI 1 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
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#endif
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};
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uint32_t marvell_get_io_win_gcr_target(int ap_index)
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{
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return PIDI_TID;
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}
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int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = io_win_memory_map;
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if (*win == NULL)
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*size = 0;
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else
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*size = ARRAY_SIZE(io_win_memory_map);
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return 0;
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}
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* IOB Configuration
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*****************************************************************************
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*/
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struct addr_map_win iob_memory_map_cp0[] = {
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/* CP0 */
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/* PEX1_X1 window */
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{0x00000000f7000000, 0x1000000, PEX1_TID},
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/* PEX2_X1 window */
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{0x00000000f8000000, 0x1000000, PEX2_TID},
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/* PEX0_X4 window */
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{0x00000000f6000000, 0x1000000, PEX0_TID},
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{0x00000000c0000000, 0x30000000, PEX0_TID},
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{0x0000000800000000, 0x100000000, PEX0_TID},
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};
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struct addr_map_win iob_memory_map_cp1[] = {
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/* CP1 */
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/* SPI1_CS0 (RUNIT) window */
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{0x00000000f9000000, 0x1000000, RUNIT_TID},
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/* PEX1_X1 window */
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{0x00000000fb000000, 0x1000000, PEX1_TID},
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/* PEX2_X1 window */
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{0x00000000fc000000, 0x1000000, PEX2_TID},
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/* PEX0_X4 window */
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{0x00000000fa000000, 0x1000000, PEX0_TID}
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};
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int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
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uintptr_t base)
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{
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switch (base) {
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case MVEBU_CP_REGS_BASE(0):
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*win = iob_memory_map_cp0;
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*size = ARRAY_SIZE(iob_memory_map_cp0);
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return 0;
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case MVEBU_CP_REGS_BASE(1):
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*win = iob_memory_map_cp1;
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*size = ARRAY_SIZE(iob_memory_map_cp1);
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return 0;
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default:
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*size = 0;
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*win = 0;
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return 1;
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}
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}
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#endif
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/*****************************************************************************
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* CCU Configuration
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*****************************************************************************
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*/
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struct addr_map_win ccu_memory_map[] = {
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#ifdef IMAGE_BLE
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{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
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#else
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#if LLC_SRAM
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{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
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#endif
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{0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
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{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
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{0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
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#endif
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};
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uint32_t marvell_get_ccu_gcr_target(int ap)
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{
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return DRAM_0_TID;
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}
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int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = ccu_memory_map;
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*size = ARRAY_SIZE(ccu_memory_map);
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return 0;
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}
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/* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */
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/*****************************************************************************
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* SKIP IMAGE Configuration
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*****************************************************************************
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*/
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void *plat_marvell_get_skip_image_data(void)
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{
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/* No recovery button on A8k-MCBIN board */
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return NULL;
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}
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@ -0,0 +1,59 @@
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/*
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* Copyright (C) 2020 Sartura Ltd.
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* Author: Luka Kovacic <luka.kovacic@sartura.hr>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <armada_common.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/ti/uart/uart_16550.h>
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#include <drivers/console.h>
|
||||||
|
#include <plat_marvell.h>
|
||||||
|
|
||||||
|
/*****************************************************************************
|
||||||
|
* Platform specific power off functions
|
||||||
|
* Power off PSU / Send command to power management MCU / ...
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
unsigned char add_xor_checksum(unsigned char *buf, unsigned char xor_len)
|
||||||
|
{
|
||||||
|
unsigned char xor_sum = 0;
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
for (i = 0; i < xor_len; i++)
|
||||||
|
xor_sum ^= buf[i];
|
||||||
|
|
||||||
|
return xor_sum;
|
||||||
|
}
|
||||||
|
|
||||||
|
int system_power_off(void)
|
||||||
|
{
|
||||||
|
static console_t console;
|
||||||
|
|
||||||
|
/* WT61P803 MCU system_off_now command */
|
||||||
|
unsigned char system_off_now[4] = { '@', 'C', '0' };
|
||||||
|
int i, len;
|
||||||
|
|
||||||
|
len = sizeof(system_off_now);
|
||||||
|
system_off_now[len - 1] = add_xor_checksum(system_off_now, len);
|
||||||
|
|
||||||
|
console_16550_register(PLAT_MARVELL_BOOT_UART_BASE + 0x100,
|
||||||
|
PLAT_MARVELL_BOOT_UART_CLK_IN_HZ, 115200, &console);
|
||||||
|
|
||||||
|
/* Send system_off_now to console */
|
||||||
|
for (i = 0; i < len; i++) {
|
||||||
|
console.putc(system_off_now[i], &console);
|
||||||
|
udelay(1000);
|
||||||
|
}
|
||||||
|
|
||||||
|
console.flush(&console);
|
||||||
|
(void)console_unregister(&console);
|
||||||
|
|
||||||
|
mdelay(100);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
|
@ -0,0 +1,17 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2018 Marvell International Ltd.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
* https://spdx.org/licenses
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MVEBU_DEF_H
|
||||||
|
#define MVEBU_DEF_H
|
||||||
|
|
||||||
|
#include <a8k_plat_def.h>
|
||||||
|
|
||||||
|
#define CP_COUNT 2 /* A80x0 has both CP0 & CP1 */
|
||||||
|
#define I2C_SPD_ADDR 0x53 /* Access SPD data */
|
||||||
|
#define I2C_SPD_P0_ADDR 0x36 /* Select SPD data page 0 */
|
||||||
|
|
||||||
|
#endif /* MVEBU_DEF_H */
|
|
@ -0,0 +1,20 @@
|
||||||
|
#
|
||||||
|
# Copyright (C) 2018 Marvell International Ltd.
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
# https://spdx.org/licenses
|
||||||
|
#
|
||||||
|
|
||||||
|
PCI_EP_SUPPORT := 0
|
||||||
|
|
||||||
|
CP_NUM := 2
|
||||||
|
$(eval $(call add_define,CP_NUM))
|
||||||
|
|
||||||
|
DOIMAGE_SEC := tools/doimage/secure/sec_img_8K.cfg
|
||||||
|
|
||||||
|
MARVELL_MOCHI_DRV := drivers/marvell/mochi/apn806_setup.c
|
||||||
|
|
||||||
|
BOARD_DIR := $(shell dirname $(lastword $(MAKEFILE_LIST)))
|
||||||
|
include plat/marvell/armada/a8k/common/a8k_common.mk
|
||||||
|
|
||||||
|
include plat/marvell/armada/common/marvell_common.mk
|
Loading…
Reference in New Issue