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Add bl2 setup code common across Broadcom platforms 

Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Change-Id: Iabeaee35c22608c93945c8295bf70947b0f6049a
This commit is contained in:
Sheetal Tigadoli 2019-12-13 10:39:06 +05:30
parent 5c38088881
commit 717448d622
26 changed files with 2966 additions and 0 deletions
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15
include/plat/brcm/common/bcm_console.h Normal file
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/*
* Copyright (c) 2018-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BCM_CONSOLE_H
#define BCM_CONSOLE_H
void bcm_console_boot_init(void);
void bcm_console_boot_end(void);
void bcm_console_runtime_init(void);
void bcm_console_runtime_end(void);
#endif /* BCM_CONSOLE_H */

153
include/plat/brcm/common/brcm_def.h Normal file
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BRCM_DEF_H
#define BRCM_DEF_H
#include <arch.h>
#include <common/tbbr/tbbr_img_def.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables.h>
#include <plat/common/common_def.h>
#include <platform_def.h>
#define PLAT_PHY_ADDR_SPACE_SIZE BIT_64(32)
#define PLAT_VIRT_ADDR_SPACE_SIZE BIT_64(32)
#define BL11_DAUTH_ID 0x796C51ab
#define BL11_DAUTH_BASE BL11_RW_BASE
/* We keep a table at the end of ROM for function pointers */
#define ROM_TABLE_SIZE 32
#define BL1_ROM_TABLE (BL1_RO_LIMIT - ROM_TABLE_SIZE)
/*
* The top 16MB of DRAM1 is configured as secure access only using the TZC
* - SCP TZC DRAM: If present, DRAM reserved for SCP use
* - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
*/
#define BRCM_TZC_DRAM1_SIZE ULL(0x01000000)
#define BRCM_SCP_TZC_DRAM1_BASE (BRCM_DRAM1_BASE + \
BRCM_DRAM1_SIZE - \
BRCM_SCP_TZC_DRAM1_SIZE)
#define BRCM_SCP_TZC_DRAM1_SIZE PLAT_BRCM_SCP_TZC_DRAM1_SIZE
#define BRCM_AP_TZC_DRAM1_BASE (BRCM_DRAM1_BASE + \
BRCM_DRAM1_SIZE - \
BRCM_TZC_DRAM1_SIZE)
#define BRCM_AP_TZC_DRAM1_SIZE (BRCM_TZC_DRAM1_SIZE - \
BRCM_SCP_TZC_DRAM1_SIZE)
#define BRCM_NS_DRAM1_BASE BRCM_DRAM1_BASE
#define BRCM_NS_DRAM1_SIZE (BRCM_DRAM1_SIZE - \
BRCM_TZC_DRAM1_SIZE)
#ifdef BRCM_SHARED_DRAM_BASE
#define BRCM_NS_SHARED_DRAM_BASE BRCM_SHARED_DRAM_BASE
#define BRCM_NS_SHARED_DRAM_SIZE BRCM_SHARED_DRAM_SIZE
#endif
#define BRCM_MAP_SHARED_RAM MAP_REGION_FLAT( \
BRCM_SHARED_RAM_BASE, \
BRCM_SHARED_RAM_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define BRCM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
BRCM_NS_DRAM1_BASE, \
BRCM_NS_DRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
#ifdef BRCM_SHARED_DRAM_BASE
#define BRCM_MAP_NS_SHARED_DRAM MAP_REGION_FLAT( \
BRCM_NS_SHARED_DRAM_BASE, \
BRCM_NS_SHARED_DRAM_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
#endif
#ifdef BRCM_EXT_SRAM_BASE
#define BRCM_MAP_EXT_SRAM MAP_REGION_FLAT( \
BRCM_EXT_SRAM_BASE, \
BRCM_EXT_SRAM_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#endif
#define BRCM_MAP_NAND_RO MAP_REGION_FLAT(NAND_BASE_ADDR,\
NAND_SIZE, \
MT_MEMORY | MT_RO | MT_SECURE)
#define BRCM_MAP_QSPI_RO MAP_REGION_FLAT(QSPI_BASE_ADDR,\
QSPI_SIZE, \
MT_MEMORY | MT_RO | MT_SECURE)
#define HSLS_REGION MAP_REGION_FLAT(HSLS_BASE_ADDR, \
HSLS_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define CCN_REGION MAP_REGION_FLAT(PLAT_BRCM_CCN_BASE, \
CCN_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define GIC500_REGION MAP_REGION_FLAT(GIC500_BASE, \
GIC500_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#ifdef PERIPH0_BASE
#define PERIPH0_REGION MAP_REGION_FLAT(PERIPH0_BASE, \
PERIPH0_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#endif
#ifdef PERIPH1_BASE
#define PERIPH1_REGION MAP_REGION_FLAT(PERIPH1_BASE, \
PERIPH1_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#endif
#ifdef PERIPH2_BASE
#define PERIPH2_REGION MAP_REGION_FLAT(PERIPH2_BASE, \
PERIPH2_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#endif
#if BRCM_BL31_IN_DRAM
#if IMAGE_BL2
#define BRCM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
BL31_BASE, \
PLAT_BRCM_MAX_BL31_SIZE,\
MT_DEVICE | MT_RW | MT_SECURE)
#else
#define BRCM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
BL31_BASE, \
PLAT_BRCM_MAX_BL31_SIZE,\
MT_MEMORY | MT_RW | MT_SECURE)
#endif
#endif
#if defined(USB_BASE) && defined(DRIVER_USB_ENABLE)
#define USB_REGION MAP_REGION_FLAT( \
USB_BASE, \
USB_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#endif
#ifdef USE_CRMU_SRAM
#define CRMU_SRAM_REGION MAP_REGION_FLAT( \
CRMU_SRAM_BASE, \
CRMU_SRAM_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#endif
/*
* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#if USE_COHERENT_MEM
#define BRCM_BL_REGIONS 3
#else
#define BRCM_BL_REGIONS 2
#endif
#endif /* BRCM_DEF_H */

30
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/*
* Copyright (c) 2019-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLAT_BRCM_H
#define PLAT_BRCM_H
#include <stdint.h>
#include <lib/cassert.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables.h>
#include <platform_def.h>
struct image_info;
/* Global variables */
extern const mmap_region_t plat_brcm_mmap[];
uint32_t brcm_get_spsr_for_bl32_entry(void);
uint32_t brcm_get_spsr_for_bl33_entry(void);
const mmap_region_t *plat_brcm_get_mmap(void);
int bcm_bl2_handle_scp_bl2(struct image_info *image_info);
void plat_brcm_io_setup(void);
void plat_brcm_process_flags(uint16_t plat_toc_flags);
#endif /* PLAT_BRCM_H */

65
plat/brcm/board/common/bcm_console.c Normal file
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/*
* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <common/debug.h>
#include <drivers/console.h>
#include <drivers/ti/uart/uart_16550.h>
#include <platform_def.h>
/*******************************************************************************
* Functions that set up the console
******************************************************************************/
static console_t bcm_boot_console;
static console_t bcm_runtime_console;
/* Initialize the console to provide early debug support */
void bcm_console_boot_init(void)
{
int rc = console_16550_register(PLAT_BRCM_BOOT_UART_BASE,
PLAT_BRCM_BOOT_UART_CLK_IN_HZ,
BRCM_CONSOLE_BAUDRATE,
&bcm_boot_console);
if (rc == 0) {
/*
* The crash console doesn't use the multi console API, it uses
* the core console functions directly. It is safe to call panic
* and let it print debug information.
*/
panic();
}
console_set_scope(&bcm_boot_console, CONSOLE_FLAG_BOOT);
}
void bcm_console_boot_end(void)
{
(void)console_flush();
(void)console_unregister(&bcm_boot_console);
}
/* Initialize the runtime console */
void bcm_console_runtime_init(void)
{
int rc = console_16550_register(PLAT_BRCM_BL31_RUN_UART_BASE,
PLAT_BRCM_BL31_RUN_UART_CLK_IN_HZ,
BRCM_CONSOLE_BAUDRATE,
&bcm_runtime_console);
if (rc == 0)
panic();
console_set_scope(&bcm_runtime_console, CONSOLE_FLAG_RUNTIME);
}
void bcm_console_runtime_end(void)
{
(void)console_flush();
(void)console_unregister(&bcm_runtime_console);
}

42
plat/brcm/board/common/board_common.c Normal file
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <brcm_def.h>
#include <plat_brcm.h>
#if IMAGE_BL2
const mmap_region_t plat_brcm_mmap[] = {
HSLS_REGION,
BRCM_MAP_SHARED_RAM,
BRCM_MAP_NAND_RO,
BRCM_MAP_QSPI_RO,
#ifdef PERIPH0_REGION
PERIPH0_REGION,
#endif
#ifdef PERIPH1_REGION
PERIPH1_REGION,
#endif
#ifdef USE_DDR
BRCM_MAP_NS_DRAM1,
#if BRCM_BL31_IN_DRAM
BRCM_MAP_BL31_SEC_DRAM,
#endif
#else
#ifdef BRCM_MAP_EXT_SRAM
BRCM_MAP_EXT_SRAM,
#endif
#endif
#if defined(USE_CRMU_SRAM) && defined(CRMU_SRAM_BASE)
CRMU_SRAM_REGION,
#endif
{0}
};
#endif
CASSERT((ARRAY_SIZE(plat_brcm_mmap) - 1) <= PLAT_BRCM_MMAP_ENTRIES,
assert_plat_brcm_mmap_mismatch);
CASSERT((PLAT_BRCM_MMAP_ENTRIES + BRCM_BL_REGIONS) <= MAX_MMAP_REGIONS,
assert_max_mmap_regions);

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#
# Copyright (c) 2015 - 2020, Broadcom
#
# SPDX-License-Identifier: BSD-3-Clause
#
PLAT_BL_COMMON_SOURCES += plat/brcm/board/common/board_common.c
# If no board config makefile, do not include it
ifneq (${BOARD_CFG},)
BOARD_CFG_MAKE := $(shell find plat/brcm/board/${PLAT} -name '${BOARD_CFG}.mk')
$(eval $(call add_define,BOARD_CFG))
ifneq (${BOARD_CFG_MAKE},)
$(info Including ${BOARD_CFG_MAKE})
include ${BOARD_CFG_MAKE}
else
$(error Error: File ${BOARD_CFG}.mk not found in plat/brcm/board/${PLAT})
endif
endif
# To compile with highest log level (VERBOSE) set value to 50
LOG_LEVEL := 40
# Use custom generic timer clock
ifneq (${GENTIMER_ACTUAL_CLOCK},)
$(info Using GENTIMER_ACTUAL_CLOCK=$(GENTIMER_ACTUAL_CLOCK))
SYSCNT_FREQ := $(GENTIMER_ACTUAL_CLOCK)
$(eval $(call add_define,SYSCNT_FREQ))
endif
ifeq (${STANDALONE_BL2},yes)
$(eval $(call add_define,MMU_DISABLED))
endif
# BL2 XIP from QSPI
RUN_BL2_FROM_QSPI := 0
ifeq (${RUN_BL2_FROM_QSPI},1)
$(eval $(call add_define,RUN_BL2_FROM_QSPI))
endif
# Use CRMU SRAM from iHOST
ifneq (${USE_CRMU_SRAM},)
$(eval $(call add_define,USE_CRMU_SRAM))
endif
# On BRCM platforms, separate the code and read-only data sections to allow
# mapping the former as executable and the latter as execute-never.
SEPARATE_CODE_AND_RODATA := 1
# Use generic OID definition (tbbr_oid.h)
USE_TBBR_DEFS := 1
PLAT_INCLUDES += -Iplat/brcm/board/common
PLAT_BL_COMMON_SOURCES += plat/brcm/common/brcm_common.c \
plat/brcm/board/common/cmn_sec.c \
plat/brcm/board/common/bcm_console.c \
plat/brcm/board/common/plat_setup.c \
plat/brcm/board/common/platform_common.c \
drivers/arm/sp804/sp804_delay_timer.c \
drivers/delay_timer/delay_timer.c \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
plat/brcm/common/brcm_io_storage.c \
plat/brcm/board/common/err.c \
drivers/arm/sp805/sp805.c
BL2_SOURCES += plat/brcm/common/brcm_bl2_mem_params_desc.c \
plat/brcm/common/brcm_image_load.c \
common/desc_image_load.c
BL2_SOURCES += plat/brcm/common/brcm_bl2_setup.c
# Use translation tables library v1 by default
ARM_XLAT_TABLES_LIB_V1 := 1
ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
PLAT_BL_COMMON_SOURCES += lib/xlat_tables/aarch64/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c
endif

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plat/brcm/board/common/cmn_plat_def.h Normal file
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/*
* Copyright (c) 2015 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CMN_PLAT_DEF_H
#define CMN_PLAT_DEF_H
/* Print file and line number on assert */
#define PLAT_LOG_LEVEL_ASSERT LOG_LEVEL_INFO
/*
* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#if USE_COHERENT_MEM
#define CMN_BL_REGIONS 3
#else
#define CMN_BL_REGIONS 2
#endif
/*
* FIP definitions
*/
#define PLAT_FIP_ATTEMPT_OFFSET 0x20000
#define PLAT_FIP_NUM_ATTEMPTS 128
#define PLAT_BRCM_FIP_QSPI_BASE QSPI_BASE_ADDR
#define PLAT_BRCM_FIP_NAND_BASE NAND_BASE_ADDR
#define PLAT_BRCM_FIP_MAX_SIZE 0x01000000
#define PLAT_BRCM_FIP_BASE PLAT_BRCM_FIP_QSPI_BASE
#endif

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plat/brcm/board/common/cmn_plat_util.h Normal file
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/*
* Copyright (c) 2015 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CMN_PLAT_UTIL_H
#define CMN_PLAT_UTIL_H
#include <lib/mmio.h>
/* BOOT source */
#define BOOT_SOURCE_MASK 7
#define BOOT_SOURCE_QSPI 0
#define BOOT_SOURCE_NAND 1
#define BOOT_SOURCE_SPI_NAND 2
#define BOOT_SOURCE_UART 3
#define BOOT_SOURCE_RES4 4
#define BOOT_SOURCE_EMMC 5
#define BOOT_SOURCE_ATE 6
#define BOOT_SOURCE_USB 7
#define BOOT_SOURCE_MAX 8
#define BOOT_SOURCE_UNKNOWN (-1)
#define KHMAC_SHA256_KEY_SIZE 32
#define SOFT_PWR_UP_RESET_L0 0
#define SOFT_SYS_RESET_L1 1
#define SOFT_RESET_L3 0x3
#define BOOT_SOURCE_SOFT_DATA_OFFSET 8
#define BOOT_SOURCE_SOFT_ENABLE_OFFSET 14
#define BOOT_SOURCE_SOFT_ENABLE_MASK BIT(BOOT_SOURCE_SOFT_ENABLE_OFFSET)
typedef struct _key {
uint8_t hmac_sha256[KHMAC_SHA256_KEY_SIZE];
} cmn_key_t;
uint32_t boot_source_get(void);
void bl1_platform_wait_events(void);
void plat_soft_reset(uint32_t reset);
#endif

49
plat/brcm/board/common/cmn_sec.c Normal file
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/*
* Copyright (c) 2015-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <cmn_sec.h>
#pragma weak plat_tz_master_default_cfg
#pragma weak plat_tz_sdio_ns_master_set
#pragma weak plat_tz_usb_ns_master_set
void plat_tz_master_default_cfg(void)
{
/* This function should be implemented in the platform side. */
ERROR("%s: TZ CONFIGURATION NOT SET!!!\n", __func__);
}
void plat_tz_sdio_ns_master_set(uint32_t ns)
{
/* This function should be implemented in the platform side. */
ERROR("%s: TZ CONFIGURATION NOT SET!!!\n", __func__);
}
void plat_tz_usb_ns_master_set(uint32_t ns)
{
/* This function should be implemented in the platform side. */
ERROR("%s: TZ CONFIGURATION NOT SET!!!\n", __func__);
}
void tz_master_default_cfg(void)
{
plat_tz_master_default_cfg();
}
void tz_sdio_ns_master_set(uint32_t ns)
{
plat_tz_sdio_ns_master_set(ns);
}
void tz_usb_ns_master_set(uint32_t ns)
{
plat_tz_usb_ns_master_set(ns);
}

19
plat/brcm/board/common/cmn_sec.h Normal file
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/*
* Copyright (c) 2015-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CMN_SEC_H
#define CMN_SEC_H
#include <stdint.h>
#define SECURE_MASTER 0
#define NS_MASTER 1
void tz_master_default_cfg(void);
void tz_usb_ns_master_set(uint32_t ns);
void tz_sdio_ns_master_set(uint32_t ns);
#endif

37
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/console.h>
#include <lib/mmio.h>
#include <platform_def.h>
#define L0_RESET 0x2
/*
* Brcm error handler
*/
void plat_error_handler(int err)
{
INFO("L0 reset...\n");
/* Ensure the characters are flushed out */
console_flush();
mmio_write_32(CRMU_SOFT_RESET_CTRL, L0_RESET);
/*
* In case we get here:
* Loop until the watchdog resets the system
*/
while (1) {
wfi();
}
}

27
plat/brcm/board/common/plat_setup.c Normal file
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/*
* Copyright (c) 2015 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/common/platform.h>
#include <platform_def.h>
/*
* This function returns the fixed clock frequency at which private
* timers run. This value will be programmed into CNTFRQ_EL0.
*/
unsigned int plat_get_syscnt_freq2(void)
{
return SYSCNT_FREQ;
}
static const char * const plat_prefix_str[] = {
"E: ", "N: ", "W: ", "I: ", "V: "
};
const char *plat_log_get_prefix(unsigned int log_level)
{
return plat_prefix_str[log_level - 1U];
}

43
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/*
* Copyright (c) 2015-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <common/debug.h>
#include <cmn_plat_util.h>
#include <platform_def.h>
uint32_t boot_source_get(void)
{
/* For now return BOOT_SOURCE_QSPI */
return BOOT_SOURCE_QSPI;
}
void __dead2 plat_soft_reset(uint32_t reset)
{
if (reset == SOFT_RESET_L3) {
mmio_setbits_32(CRMU_IHOST_SW_PERSISTENT_REG1, reset);
mmio_write_32(CRMU_MAIL_BOX0, 0x0);
mmio_write_32(CRMU_MAIL_BOX1, 0xFFFFFFFF);
}
if (reset != SOFT_SYS_RESET_L1)
reset = SOFT_PWR_UP_RESET_L0;
if (reset == SOFT_PWR_UP_RESET_L0)
INFO("L0 RESET...\n");
if (reset == SOFT_SYS_RESET_L1)
INFO("L1 RESET...\n");
console_flush();
mmio_clrbits_32(CRMU_SOFT_RESET_CTRL, 1 << reset);
while (1) {
;
}
}

263
plat/brcm/board/stingray/aarch64/plat_helpers.S Normal file
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/*
* Copyright (c) 2015-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
#include <cpu_macros.S>
#include <cortex_a72.h>
#include <drivers/ti/uart/uart_16550.h>
#include <platform_def.h>
.globl plat_reset_handler
.globl platform_get_entrypoint
.globl plat_secondary_cold_boot_setup
.globl platform_mem_init
.globl platform_check_mpidr
.globl plat_crash_console_init
.globl plat_crash_console_putc
.globl plat_crash_console_flush
.globl plat_disable_acp
.globl plat_is_my_cpu_primary
.globl plat_my_core_pos
.globl platform_is_primary_cpu
.globl plat_brcm_calc_core_pos
.globl plat_get_my_entrypoint
/* ------------------------------------------------------------
* void plat_l2_init(void);
*
* BL1 and BL2 run with one core, one cluster
* This is safe to disable cluster coherency
* to make use of the data cache MMU WB attribute
* for the SRAM.
*
* Set L2 Auxiliary Control Register
* --------------------------------------------------------------------
*/
func plat_l2_init
mrs x0, CORTEX_A72_L2ACTLR_EL1
#if (IMAGE_BL1 || IMAGE_BL2) || defined(USE_SINGLE_CLUSTER)
orr x0, x0, #CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI
#else
bic x0, x0, #CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI
#endif
msr CORTEX_A72_L2ACTLR_EL1, x0
/* Set L2 Control Register */
mrs x0, CORTEX_A72_L2CTLR_EL1
mov x1, #((CORTEX_A72_L2_DATA_RAM_LATENCY_MASK << \
CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
(CORTEX_A72_L2_TAG_RAM_LATENCY_MASK << \
CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT) | \
(U(0x1) << CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT) | \
(U(0x1) << CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT))
bic x0, x0, x1
mov x1, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << \
CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
(U(0x1) << CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT) | \
(U(0x1) << CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT))
orr x0, x0, x1
msr CORTEX_A72_L2CTLR_EL1, x0
isb
ret
endfunc plat_l2_init
/* --------------------------------------------------------------------
* void plat_reset_handler(void);
*
* Before adding code in this function, refer to the guidelines in
* docs/firmware-design.md.
*
* --------------------------------------------------------------------
*/
func plat_reset_handler
mov x9, x30
bl plat_l2_init
mov x30, x9
ret
endfunc plat_reset_handler
/* -----------------------------------------------------
* void platform_get_entrypoint (unsigned int mpid);
*
* Main job of this routine is to distinguish between
* a cold and warm boot.
* On a cold boot the secondaries first wait for the
* platform to be initialized after which they are
* hotplugged in. The primary proceeds to perform the
* platform initialization.
* -----------------------------------------------------
*/
func platform_get_entrypoint
/*TBD-STINGRAY*/
mov x0, #0
ret
endfunc platform_get_entrypoint
/* -----------------------------------------------------
* void plat_secondary_cold_boot_setup (void);
*
* This function performs any platform specific actions
* needed for a secondary cpu after a cold reset e.g
* mark the cpu's presence, mechanism to place it in a
* holding pen etc.
* -----------------------------------------------------
*/
func plat_secondary_cold_boot_setup
bl plat_my_core_pos
mov_imm x1, SECONDARY_CPU_SPIN_BASE_ADDR
add x0, x1, x0, LSL #3
mov x1, #0
str x1, [x0]
/* Wait until the entrypoint gets populated */
poll_mailbox:
ldr x1, [x0]
cbz x1, 1f
br x1
1:
wfe
b poll_mailbox
endfunc plat_secondary_cold_boot_setup
/* -----------------------------------------------------
* void platform_mem_init(void);
*
* We don't need to carry out any memory initialization
* on CSS platforms. The Secure RAM is accessible straight away.
* -----------------------------------------------------
*/
func platform_mem_init
/*TBD-STINGRAY*/
ret
endfunc platform_mem_init
/* -----------------------------------------------------
* Placeholder function which should be redefined by
* each platform.
* -----------------------------------------------------
*/
func platform_check_mpidr
/*TBD-STINGRAY*/
mov x0, xzr
ret
endfunc platform_check_mpidr
/* ---------------------------------------------
* int plat_crash_console_init(void)
* Function to initialize the crash console
* without a C Runtime to print crash report.
* Clobber list : x0, x1, x2
* ---------------------------------------------
*/
func plat_crash_console_init
mov_imm x0, BRCM_CRASH_CONSOLE_BASE
mov_imm x1, BRCM_CRASH_CONSOLE_REFCLK
mov_imm x2, BRCM_CRASH_CONSOLE_BAUDRATE
b console_16550_core_init
ret
endfunc plat_crash_console_init
/* ---------------------------------------------
* int plat_crash_console_putc(void)
* Function to print a character on the crash
* console without a C Runtime.
* Clobber list : x1, x2, x3
* ---------------------------------------------
*/
func plat_crash_console_putc
mov_imm x1, BRCM_CRASH_CONSOLE_BASE
b console_16550_core_putc
ret
endfunc plat_crash_console_putc
/* ---------------------------------------------
* int plat_crash_console_flush(void)
* Function to flush crash console
* Clobber list : x0, x1
* ---------------------------------------------
*/
func plat_crash_console_flush
mov_imm x0, BRCM_CRASH_CONSOLE_BASE
b console_16550_core_flush
ret
endfunc plat_crash_console_flush
/* -----------------------------------------------------
* Placeholder function which should be redefined by
* each platform. This function is allowed to use
* registers x0 - x17.
* -----------------------------------------------------
*/
func plat_disable_acp
/*TBD-STINGRAY*/
ret
endfunc plat_disable_acp
/* -----------------------------------------------------
* unsigned int plat_is_my_cpu_primary (void);
*
* Find out whether the current cpu is the primary
* cpu (applicable only after a cold boot)
* -----------------------------------------------------
*/
func plat_is_my_cpu_primary
mrs x0, mpidr_el1
b platform_is_primary_cpu
endfunc plat_is_my_cpu_primary
/* -----------------------------------------------------
* unsigned int plat_my_core_pos(void)
* This function uses the plat_brcm_calc_core_pos()
* definition to get the index of the calling CPU.
* -----------------------------------------------------
*/
func plat_my_core_pos
mrs x0, mpidr_el1
b plat_brcm_calc_core_pos
endfunc plat_my_core_pos
/* -----------------------------------------------------
* unsigned int platform_is_primary_cpu (void);
*
* Find out whether the current cpu is the primary
* cpu (applicable only after a cold boot)
* -----------------------------------------------------
*/
func platform_is_primary_cpu
mov x9, x30
bl plat_my_core_pos
cmp x0, #PRIMARY_CPU
cset x0, eq
ret x9
endfunc platform_is_primary_cpu
/* -----------------------------------------------------
* unsigned int plat_brcm_calc_core_pos(uint64_t mpidr)
* Helper function to calculate the core position.
* With this function: CorePos = (ClusterId * 4) +
* CoreId
* -----------------------------------------------------
*/
func plat_brcm_calc_core_pos
and x1, x0, #MPIDR_CPU_MASK
and x0, x0, #MPIDR_CLUSTER_MASK
add x0, x1, x0, LSR #7
ret
endfunc plat_brcm_calc_core_pos
func plat_get_my_entrypoint
mrs x0, mpidr_el1
b platform_get_entrypoint
endfunc plat_get_my_entrypoint

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#
# Copyright (c) 2015 - 2020, Broadcom
#
# SPDX-License-Identifier: BSD-3-Clause
#
#######################################################
# Board config file for bcm958742t-ns3 Stingray SST100-NS3
#######################################################
include plat/brcm/board/stingray/bcm958742t.mk
# Load BL33 at 0xFF00_0000 address
ifneq (${BL33_OVERRIDE_LOAD_ADDR},)
$(eval $(call add_define_val,BL33_OVERRIDE_LOAD_ADDR,0xFF000000))
endif

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#
# Copyright (c) 2015 - 2020, Broadcom
#
# SPDX-License-Identifier: BSD-3-Clause
#
#######################################################
# Board config file for bcm958742t Stingray SST100
#######################################################
BOARD_FAMILY := "<bcm958742t.h>"
$(eval $(call add_define,BOARD_FAMILY))
# Board has internal programmable regulator
IHOST_REG_TYPE := IHOST_REG_INTEGRATED
$(eval $(call add_define,IHOST_REG_TYPE))
# Board has internal programmable regulator
VDDC_REG_TYPE := VDDC_REG_INTEGRATED
$(eval $(call add_define,VDDC_REG_TYPE))

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/*
* Copyright (c) 2019-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CRMU_DEF_H
#define CRMU_DEF_H
#define CRMU_REGS_BASE 0x66410000
/* 32 kB IDRAM */
#define CRMU_IDRAM_BASE_ADDR CRMU_REGS_BASE
#define CRMU_IDRAM_SIZE 0x8000
/* 4 kB Scratch RAM */
#define CRMU_SRAM_BASE (CRMU_IDRAM_BASE_ADDR + CRMU_IDRAM_SIZE)
#define CRMU_SRAM_SIZE 0x1000
#define CRMU_RESERVED_SPACE 0x3000
#define CRMU_CORE_BASE (CRMU_SRAM_BASE + CRMU_SRAM_SIZE + \
CRMU_RESERVED_SPACE)
#define CRMU_SHARED_SRAM_BASE CRMU_SRAM_BASE
#define CRMU_SHARED_SRAM_SIZE 0x200
#define CRMU_CFG_BASE (CRMU_SHARED_SRAM_BASE + \
CRMU_SHARED_SRAM_SIZE)
#define CRMU_PWR_GOOD_STATUS CRMU_CORE_BASE
#define CRMU_PWR_GOOD_STATUS__BBL_POWER_GOOD 0
#define CRMU_ISO_CELL_CONTROL (CRMU_CORE_BASE + 0x4)
#define CRMU_ISO_CELL_CONTROL__CRMU_ISO_PDBBL 16
#define CRMU_ISO_CELL_CONTROL__CRMU_ISO_PDBBL_TAMPER 24
#define CRMU_SPRU_SOURCE_SEL_STAT (CRMU_CORE_BASE + 0xc)
#define CRMU_SPRU_SOURCE_SEL_STAT__SPRU_SOURCE_SELECT 0
#define BSTI_BASE (CRMU_CORE_BASE + 0x28)
#define BSTI_CONTROL_OFFSET BSTI_BASE
#define BSTI_COMMAND_OFFSET (BSTI_BASE + 0x4)
#define OCOTP_REGS_BASE (CRMU_CORE_BASE + 0x400)
#define CRMU_TCI_BASE (CRMU_CORE_BASE + 0x800)
#define CRMU_SWREG_STATUS_ADDR (CRMU_TCI_BASE + 0x0c)
#define CRMU_CHIP_OTPC_STATUS (CRMU_TCI_BASE + 0x10)
#define CRMU_CHIP_OTPC_STATUS__OTP_BISR_LOAD_DONE 19
#define CRMU_BISR_PDG_MASK (CRMU_TCI_BASE + 0x4c)
#define CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST0 2
#define CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST1 3
#define CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST2 4
#define CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST3 0
#define CRMU_POWER_POLL (CRMU_TCI_BASE + 0x60)
#define CRMU_OTP_STATUS CRMU_POWER_POLL
#define CRMU_OTP_STATUS_BIT 1
#define CRMU_DDR_PHY_AON_CTRL (CRMU_TCI_BASE + 0x64)
#define CRMU_DDRPHY2_HW_RESETN_R BIT(21)
#define CRMU_DDRPHY2_PWROKIN_PHY_R BIT(20)
#define CRMU_DDRPHY2_PWRONIN_PHY_R BIT(19)
#define CRMU_DDRPHY2_ISO_PHY_DFI_R BIT(18)
#define CRMU_DDRPHY2_ISO_PHY_REGS_R BIT(17)
#define CRMU_DDRPHY2_ISO_PHY_PLL_R BIT(16)
#define CRMU_DDRPHY1_HW_RESETN_R BIT(13)
#define CRMU_DDRPHY1_PWROKIN_PHY_R BIT(12)
#define CRMU_DDRPHY1_PWRONIN_PHY_R BIT(11)
#define CRMU_DDRPHY1_ISO_PHY_DFI_R BIT(10)
#define CRMU_DDRPHY1_ISO_PHY_REGS_R BIT(9)
#define CRMU_DDRPHY1_ISO_PHY_PLL_R BIT(8)
#define CRMU_DDRPHY0_HW_RESETN_R BIT(5)
#define CRMU_DDRPHY0_PWROKIN_PHY_R BIT(4)
#define CRMU_DDRPHY0_PWRONIN_PHY_R BIT(3)
#define CRMU_DDRPHY0_ISO_PHY_DFI_R BIT(2)
#define CRMU_DDRPHY0_ISO_PHY_REGS_R BIT(1)
#define CRMU_DDRPHY0_ISO_PHY_PLL_R BIT(0)
#define CRMU_EMEM_RESET_N_R BIT(16)
#define CRMU_EMEM_PRESET_N_R BIT(0)
#define CRMU_SWREG_CTRL_ADDR (CRMU_TCI_BASE + 0x6c)
#define CRMU_AON_CTRL1 (CRMU_TCI_BASE + 0x70)
#define CRMU_AON_CTRL1__LCPLL1_ISO_IN 18
#define CRMU_AON_CTRL1__LCPLL1_PWRON_LDO 19
#define CRMU_AON_CTRL1__LCPLL1_PWR_ON 20
#define CRMU_AON_CTRL1__LCPLL0_ISO_IN 21
#define CRMU_AON_CTRL1__LCPLL0_PWRON_LDO 22
#define CRMU_AON_CTRL1__LCPLL0_PWR_ON 23
#define CRMU_PCIE_LCPLL_PWR_ON_SHIFT 29
#define CRMU_PCIE_LCPLL_PWR_ON_MASK BIT(CRMU_PCIE_LCPLL_PWR_ON_SHIFT)
#define CRMU_PCIE_LCPLL_PWRON_LDO_SHIFT 28
#define CRMU_PCIE_LCPLL_PWRON_LDO_MASK BIT(CRMU_PCIE_LCPLL_PWRON_LDO_SHIFT)
#define CRMU_PCIE_LCPLL_ISO_IN_SHIFT 27
#define CRMU_PCIE_LCPLL_ISO_IN_MASK BIT(CRMU_PCIE_LCPLL_ISO_IN_SHIFT)
#define CRMU_MASTER_AXI_ARUSER_CONFIG (CRMU_TCI_BASE + 0x74)
#define CRMU_MASTER_AXI_AWUSER_CONFIG (CRMU_TCI_BASE + 0x78)
#define CRMU_DDR_PHY_AON_CTRL_1 (CRMU_TCI_BASE + 0x8c)
#define CDRU_BASE_ADDR (CRMU_CORE_BASE + 0x1000)
#define CDRU_MISC_RESET_CONTROL CDRU_BASE_ADDR
#define CDRU_MISC_RESET_CONTROL_TS_RESET_N 16
#define CDRU_MISC_RESET_CONTROL__CDRU_USBSS_RESET_N 14
#define CDRU_MISC_RESET_CONTROL__CDRU_SATA_RESET_N_R 15
#define CDRU_MISC_RESET_CONTROL__CDRU_MHB_RESET_N_R 13
#define CDRU_MISC_RESET_CONTROL__CDRU_PCIE_RESET_N_R 3
#define CDRU_MISC_RESET_CONTROL__CDRU_PM_RESET_N_R 2
#define CDRU_MISC_RESET_CONTROL__CDRU_NITRO_RESET_N_R 1
#define CDRU_PROC_EVENT_CLEAR (CDRU_BASE_ADDR + 0x48)
#define CDRU_PROC_EVENT_CLEAR__IH0_CDRU_STANDBYWFIL2 0
#define CDRU_PROC_EVENT_CLEAR__IH0_CDRU_STANDBYWFI 3
#define CDRU_PROC_EVENT_CLEAR__IH1_CDRU_STANDBYWFIL2 5
#define CDRU_PROC_EVENT_CLEAR__IH1_CDRU_STANDBYWFI 8
#define CDRU_PROC_EVENT_CLEAR__IH2_CDRU_STANDBYWFIL2 10
#define CDRU_PROC_EVENT_CLEAR__IH2_CDRU_STANDBYWFI 13
#define CDRU_PROC_EVENT_CLEAR__IH3_CDRU_STANDBYWFIL2 15
#define CDRU_PROC_EVENT_CLEAR__IH3_CDRU_STANDBYWFI 18
#define CDRU_CHIP_STRAP_CTRL (CDRU_BASE_ADDR + 0x50)
#define CDRU_CHIP_STRAP_CTRL__SOFTWARE_OVERRIDE 31
#define CDRU_CHIP_IO_PAD_CONTROL (CDRU_BASE_ADDR + 0x58)
#define CDRU_CHIP_IO_PAD_CONTROL__CDRU_IOMUX_FORCE_PDN_R 8
#define CDRU_CHIP_IO_PAD_CONTROL__CDRU_IOMUX_FORCE_PAD_IN_R 0
#define CDRU_CHIP_STRAP_DATA_LSW (CDRU_BASE_ADDR + 0x5c)
#define CDRU_CHIP_STRAP_DATA_LSW__BISR_BYPASS_MODE 18
#define CDRU_CHIP_STRAP_DATA_LSW__NIC_MODE_MASK BIT(8)
#define CDRU_CHIP_STRAP_DATA_LSW_PAD_USB_MODE BIT(26)
#define CDRU_CHIP_STRAP_DATA (CDRU_BASE_ADDR + 0x5c)
#define CDRU_DDR0_CONTROL_OFFSET (CDRU_BASE_ADDR + 0xb8)
#define CDRU_DDR1_CONTROL_OFFSET (CDRU_BASE_ADDR + 0xbc)
#define CDRU_DDR2_CONTROL_OFFSET (CDRU_BASE_ADDR + 0xc0)
#define CRMU_SW_POR_RESET_CTRL (CDRU_BASE_ADDR + 0x100)
#define CDRU_GENPLL2_CONTROL1 (CDRU_BASE_ADDR + 0x1b0)
#define CDRU_GENPLL2_CONTROL1__CHNL6_FS4_CLK BIT(11)
#define CDRU_GENPLL5_CONTROL1 (CDRU_BASE_ADDR + 0x24c)
#define CDRU_GENPLL5_CONTROL1__CHNL0_DME_CLK BIT(6)
#define CDRU_GENPLL5_CONTROL1__CHNL1_CRYPTO_AE_CLK BIT(7)
#define CDRU_GENPLL5_CONTROL1__CHNL2_RAID_AE_CLK BIT(8)
#define CDRU_NITRO_CONTROL (CDRU_BASE_ADDR + 0x2c4)
#define CDRU_NITRO_CONTROL__CDRU_NITRO_SEC_MODE_R 20
#define CDRU_NITRO_CONTROL__CDRU_NITRO_SEC_OVERRIDE_R 16
#define CDRU_MISC_CLK_ENABLE_CONTROL (CDRU_BASE_ADDR + 0x2c8)
#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_EMEM2_CLK_EN_R 11
#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_EMEM1_CLK_EN_R 10
#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_EMEM0_CLK_EN_R 9
#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_SATA_CLK_EN_R 8
#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_USBSS_CLK_EN_R 7
#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_MHB_CLK_EN_R 6
#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_HSLS_CLK_EN_R 5
#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_SCR_CLK_EN_R 4
#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_FS4_CLK_EN_R 3
#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_PCIE_CLK_EN_R 2
#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_PM_CLK_EN_R 1
#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_NITRO_CLK_EN_R 0
#define CDRU_CCN_REGISTER_CONTROL_1 (CDRU_BASE_ADDR + 0x324)
#define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_EMEM0_BIT 6
#define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_EMEM1_BIT 5
#define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_EMEM2_BIT 4
#define CDRU_CHIP_TOP_SPARE_REG0 (CDRU_BASE_ADDR + 0x378)
#define CDRU_CHIP_TOP_SPARE_REG1 (CDRU_BASE_ADDR + 0x37c)
#define CENTRAL_TIMER_BASE (CRMU_CORE_BASE + 0x5000)
#define CENTRAL_TIMER_CTRL (CENTRAL_TIMER_BASE + 0x0)
#define CENTRAL_TIMER_GET_L (CENTRAL_TIMER_BASE + 0x4)
#define CENTRAL_TIMER_GET_L0 (CENTRAL_TIMER_BASE + 0x8) /* SCR STM */
#define CENTRAL_TIMER_GET_L1 (CENTRAL_TIMER_BASE + 0xC) /* FS STM */
#define CENTRAL_TIMER_GET_L2 (CENTRAL_TIMER_BASE + 0x10) /* iHost0 */
#define CENTRAL_TIMER_GET_L3 (CENTRAL_TIMER_BASE + 0x14) /* iHost1 */
#define CENTRAL_TIMER_GET_L4 (CENTRAL_TIMER_BASE + 0x18) /* iHost2 */
#define CENTRAL_TIMER_GET_L5 (CENTRAL_TIMER_BASE + 0x1C) /* iHost3 */
#define CENTRAL_TIMER_GET_H (CENTRAL_TIMER_BASE + 0x28)
#define CENTRAL_TIMER_SAT_TMR_ENA (CENTRAL_TIMER_BASE + 0x34)
#define CENTRAL_TIMER_GET_IHOST_ENA_BASE (CENTRAL_TIMER_GET_L2)
#define CRMU_WDT_REGS_BASE (CRMU_CORE_BASE + 0x6000)
#define CRMU_MAIL_BOX0 (CRMU_CORE_BASE + 0x8024)
#define CRMU_MAIL_BOX1 (CRMU_CORE_BASE + 0x8028)
#define CRMU_READ_MAIL_BOX0 (CRMU_CORE_BASE + 0x802c)
#define CRMU_READ_MAIL_BOX1 (CRMU_CORE_BASE + 0x8030)
#define AP_TO_SCP_MAILBOX1 CRMU_MAIL_BOX1
#define SCP_TO_AP_MAILBOX1 CRMU_READ_MAIL_BOX1
#define CRMU_IHOST_POWER_CONFIG (CRMU_CORE_BASE + 0x8038)
#define CRMU_RESET_EVENT_LOG (CRMU_CORE_BASE + 0x8064)
#define CRMU_SOFT_RESET_CTRL (CRMU_CORE_BASE + 0x8090)
#define CRMU_SOFT_RESET_CTRL__SOFT_PWR_UP_RST 0
#define CRMU_SOFT_RESET_CTRL__SOFT_SYS_RST 1
#define CRMU_SPARE_REG_0 (CRMU_CORE_BASE + 0x80b8)
#define CRMU_SPARE_REG_1 (CRMU_CORE_BASE + 0x80bc)
#define CRMU_SPARE_REG_2 (CRMU_CORE_BASE + 0x80c0)
#define CRMU_SPARE_REG_3 (CRMU_CORE_BASE + 0x80c4)
#define CRMU_SPARE_REG_4 (CRMU_CORE_BASE + 0x80c8)
#define CRMU_SPARE_REG_5 (CRMU_CORE_BASE + 0x80cc)
#define CRMU_CORE_ADDR_RANGE0_LOW (CRMU_CORE_BASE + 0x8c30)
#define CRMU_CORE_ADDR_RANGE1_LOW (CRMU_CORE_BASE + 0x8c38)
#define CRMU_CORE_ADDR_RANGE2_LOW (CRMU_CORE_BASE + 0x8c40)
#define CRMU_IHOST_SW_PERSISTENT_REG0 (CRMU_CORE_BASE + 0x8c54)
#define CRMU_IHOST_SW_PERSISTENT_REG1 (CRMU_CORE_BASE + 0x8c58)
#define CRMU_IHOST_SW_PERSISTENT_REG2 (CRMU_CORE_BASE + 0x8c5c)
#define CRMU_IHOST_SW_PERSISTENT_REG3 (CRMU_CORE_BASE + 0x8c60)
#define CRMU_IHOST_SW_PERSISTENT_REG4 (CRMU_CORE_BASE + 0x8c64)
#define CRMU_IHOST_SW_PERSISTENT_REG5 (CRMU_CORE_BASE + 0x8c68)
#define CRMU_IHOST_SW_PERSISTENT_REG6 (CRMU_CORE_BASE + 0x8c6c)
#define CRMU_IHOST_SW_PERSISTENT_REG7 (CRMU_CORE_BASE + 0x8c70)
#define CRMU_BBL_AUTH_CHECK (CRMU_CORE_BASE + 0x8c78)
#define CRMU_SOTP_NEUTRALIZE_ENABLE (CRMU_CORE_BASE + 0x8c84)
#define CRMU_IHOST_SW_PERSISTENT_REG8 (CRMU_CORE_BASE + 0x8c88)
#define CRMU_IHOST_SW_PERSISTENT_REG9 (CRMU_CORE_BASE + 0x8c8c)
#define CRMU_IHOST_SW_PERSISTENT_REG10 (CRMU_CORE_BASE + 0x8c90)
#define CRMU_IHOST_SW_PERSISTENT_REG11 (CRMU_CORE_BASE + 0x8c94)
#define CNT_CONTROL_BASE (CRMU_CORE_BASE + 0x9000)
#define CNTCR (CNT_CONTROL_BASE)
#define CNTCR__EN BIT(0)
#define SPRU_BBL_WDATA (CRMU_CORE_BASE + 0xa000)
#define SPRU_BBL_CMD (CRMU_CORE_BASE + 0xa004)
#define SPRU_BBL_CMD__IND_SOFT_RST_N 10
#define SPRU_BBL_CMD__IND_WR 11
#define SPRU_BBL_CMD__BBL_ADDR_R 0
#define SPRU_BBL_CMD__IND_RD 12
#define SPRU_BBL_CMD__BBL_ADDR_R 0
#define SPRU_BBL_STATUS (CRMU_CORE_BASE + 0xa008)
#define SPRU_BBL_STATUS__ACC_DONE 0
#define SPRU_BBL_RDATA (CRMU_CORE_BASE + 0xa00c)
#endif /* CRMU_DEF_H */

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/*
* Copyright (c) 2015-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLAT_MACROS_S
#define PLAT_MACROS_S
.section .rodata.gic_reg_name, "aS"
gicc_regs:
.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
gicd_pend_reg:
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
newline:
.asciz "\n"
spacer:
.asciz ":\t\t0x"
/* ---------------------------------------------
* The below required platform porting macro
* prints out relevant registers whenever an
* unhandled exception is taken in BL31.
* ---------------------------------------------
*/
.macro plat_crash_print_regs
nop
.endm
/* ---------------------------------------------
* The below macro prints out relevant GIC
* registers whenever an unhandled exception is
* taken in BL31.
* ---------------------------------------------
*/
.macro plat_print_gic_regs
nop
/*TBD-STINGRAY*/
.endm
/* ------------------------------------------------
* The below required platform porting macro prints
* out relevant interconnect registers whenever an
* unhandled exception is taken in BL3-1.
* ------------------------------------------------
*/
.macro plat_print_interconnect_regs
nop
/*TBD-STINGRAY*/
.endm
#endif /* PLAT_MACROS_S */

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/*
* Copyright (c) 2015-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <arch.h>
#include <common/tbbr/tbbr_img_def.h>
#include <plat/common/common_def.h>
#include <brcm_def.h>
#include <cmn_plat_def.h>
#include "sr_def.h"
/*
* Most platform porting definitions provided by included headers
*/
#define PLAT_BRCM_SCP_TZC_DRAM1_SIZE ULL(0x0)
/*
* Required by standard platform porting definitions
*/
#define PLATFORM_CLUSTER0_CORE_COUNT 2
#define PLATFORM_CLUSTER1_CORE_COUNT 2
#define PLATFORM_CLUSTER2_CORE_COUNT 2
#define PLATFORM_CLUSTER3_CORE_COUNT 2
#define PLATFORM_CLUSTER4_CORE_COUNT 2
#define BRCM_SYSTEM_COUNT 1
#define BRCM_CLUSTER_COUNT 5
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
PLATFORM_CLUSTER1_CORE_COUNT+ \
PLATFORM_CLUSTER2_CORE_COUNT+ \
PLATFORM_CLUSTER3_CORE_COUNT+ \
PLATFORM_CLUSTER4_CORE_COUNT)
#define PLAT_NUM_PWR_DOMAINS (BRCM_SYSTEM_COUNT + \
BRCM_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT)
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/* TBD-STINGRAY */
#define CACHE_WRITEBACK_SHIFT 6
/*
* Some data must be aligned on the biggest cache line size in the platform.
* This is known only to the platform as it might have a combination of
* integrated and external caches.
*/
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
/* TBD-STINGRAY */
#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
#define BL1_PLATFORM_STACK_SIZE 0x3300
#define BL2_PLATFORM_STACK_SIZE 0xc000
#define BL11_PLATFORM_STACK_SIZE 0x2b00
#define DEFAULT_PLATFORM_STACK_SIZE 0x400
#if IMAGE_BL1
# define PLATFORM_STACK_SIZE BL1_PLATFORM_STACK_SIZE
#else
#if IMAGE_BL2
#ifdef USE_BL1_RW
# define PLATFORM_STACK_SIZE BL2_PLATFORM_STACK_SIZE
#else
# define PLATFORM_STACK_SIZE BL1_PLATFORM_STACK_SIZE
#endif
#else
#if IMAGE_BL11
# define PLATFORM_STACK_SIZE BL11_PLATFORM_STACK_SIZE
#else
# define PLATFORM_STACK_SIZE DEFAULT_PLATFORM_STACK_SIZE
#endif
#endif
#endif
#define PLAT_BRCM_TRUSTED_SRAM_BASE 0x66D00000
#define PLAT_BRCM_TRUSTED_SRAM_SIZE 0x00040000
#ifdef RUN_BL1_FROM_QSPI /* BL1 XIP from QSPI */
# define PLAT_BRCM_TRUSTED_ROM_BASE QSPI_BASE_ADDR
#elif RUN_BL1_FROM_NAND /* BL1 XIP from NAND */
# define PLAT_BRCM_TRUSTED_ROM_BASE NAND_BASE_ADDR
#else /* BL1 executed in ROM */
# define PLAT_BRCM_TRUSTED_ROM_BASE ROM_BASE_ADDR
#endif
#define PLAT_BRCM_TRUSTED_ROM_SIZE 0x00040000
/*******************************************************************************
* BL1 specific defines.
******************************************************************************/
#define BL1_RO_BASE PLAT_BRCM_TRUSTED_ROM_BASE
#define BL1_RO_LIMIT (PLAT_BRCM_TRUSTED_ROM_BASE \
+ PLAT_BRCM_TRUSTED_ROM_SIZE)
/*
* Put BL1 RW at the beginning of the Trusted SRAM.
*/
#define BL1_RW_BASE (BRCM_BL_RAM_BASE)
#define BL1_RW_LIMIT (BL1_RW_BASE + 0x12000)
#define BL11_RW_BASE BL1_RW_LIMIT
#define BL11_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \
PLAT_BRCM_TRUSTED_SRAM_SIZE)
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
#if RUN_BL2_FROM_QSPI /* BL2 XIP from QSPI */
#define BL2_BASE QSPI_BASE_ADDR
#define BL2_LIMIT (BL2_BASE + 0x40000)
#define BL2_RW_BASE BL1_RW_LIMIT
#define BL2_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \
PLAT_BRCM_TRUSTED_SRAM_SIZE)
#elif RUN_BL2_FROM_NAND /* BL2 XIP from NAND */
#define BL2_BASE NAND_BASE_ADDR
#define BL2_LIMIT (BL2_BASE + 0x40000)
#define BL2_RW_BASE BL1_RW_LIMIT
#define BL2_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \
PLAT_BRCM_TRUSTED_SRAM_SIZE)
#else
#define BL2_BASE (BL1_RW_LIMIT + PAGE_SIZE)
#define BL2_LIMIT (BRCM_BL_RAM_BASE + BRCM_BL_RAM_SIZE)
#endif
/*
* BL1 persistent area in internal SRAM
* This area will increase as more features gets into BL1
*/
#define BL1_PERSISTENT_DATA_SIZE 0x2000
/* To reduce BL2 runtime footprint, we can re-use some BL1_RW area */
#define BL1_RW_RECLAIM_BASE (PLAT_BRCM_TRUSTED_SRAM_BASE + \
BL1_PERSISTENT_DATA_SIZE)
/*******************************************************************************
* BL3-1 specific defines.
******************************************************************************/
/* Max Size of BL31 (in DRAM) */
#define PLAT_BRCM_MAX_BL31_SIZE 0x30000
#ifdef USE_DDR
#define BL31_BASE BRCM_AP_TZC_DRAM1_BASE
#define BL31_LIMIT (BRCM_AP_TZC_DRAM1_BASE + \
PLAT_BRCM_MAX_BL31_SIZE)
#else
/* Put BL3-1 at the end of external on-board SRAM connected as NOR flash */
#define BL31_BASE (NOR_BASE_ADDR + NOR_SIZE - \
PLAT_BRCM_MAX_BL31_SIZE)
#define BL31_LIMIT (NOR_BASE_ADDR + NOR_SIZE)
#endif
#define SECURE_DDR_END_ADDRESS BL31_LIMIT
#ifdef NEED_SCP_BL2
#define SCP_BL2_BASE BL31_BASE
#define PLAT_MAX_SCP_BL2_SIZE 0x9000
#define PLAT_SCP_COM_SHARED_MEM_BASE (CRMU_SHARED_SRAM_BASE)
/* dummy defined */
#define PLAT_BRCM_MHU_BASE 0x0
#endif
#define SECONDARY_CPU_SPIN_BASE_ADDR BRCM_SHARED_RAM_BASE
/* Generic system timer counter frequency */
#ifndef SYSCNT_FREQ
#define SYSCNT_FREQ (125 * 1000 * 1000)
#endif
/*
* Enable the BL32 definitions, only when optee os is selected as secure
* payload (BL32).
*/
#ifdef SPD_opteed
/*
* Reserved Memory Map : SHMEM & TZDRAM.
*
* +--------+----------+ 0x8D000000
* | SHMEM (NS) | 16MB
* +-------------------+ 0x8E000000
* | | TEE_RAM(S)| 4MB
* + TZDRAM +----------+ 0x8E400000
* | | TA_RAM(S) | 12MB
* +-------------------+ 0x8F000000
* | BL31 Binary (S) | 192KB
* +-------------------+ 0x8F030000
*/
#define BL32_VA_SIZE (4 * 1024 * 1024)
#define BL32_BASE (0x8E000000)
#define BL32_LIMIT (BL32_BASE + BL32_VA_SIZE)
#define TSP_SEC_MEM_BASE BL32_BASE
#define TSP_SEC_MEM_SIZE BL32_VA_SIZE
#endif
#ifdef SPD_opteed
#define SECURE_DDR_BASE_ADDRESS BL32_BASE
#else
#define SECURE_DDR_BASE_ADDRESS BL31_BASE
#endif
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define MAX_XLAT_TABLES 7
#define PLAT_BRCM_MMAP_ENTRIES 10
#define MAX_MMAP_REGIONS (PLAT_BRCM_MMAP_ENTRIES + \
BRCM_BL_REGIONS)
#ifdef USE_DDR
#ifdef BL33_OVERRIDE_LOAD_ADDR
#define PLAT_BRCM_NS_IMAGE_OFFSET BL33_OVERRIDE_LOAD_ADDR
#else
/*
* BL3-3 image starting offset.
* Putting start of DRAM as of now.
*/
#define PLAT_BRCM_NS_IMAGE_OFFSET 0x80000000
#endif /* BL33_OVERRIDE_LOAD_ADDR */
#else
/*
* BL3-3 image starting offset.
* Putting start of external on-board SRAM as of now.
*/
#define PLAT_BRCM_NS_IMAGE_OFFSET NOR_BASE_ADDR
#endif /* USE_DDR */
/******************************************************************************
* Required platform porting definitions common to all BRCM platforms
*****************************************************************************/
#define MAX_IO_DEVICES 5
#define MAX_IO_HANDLES 6
#define PRIMARY_CPU 0
/* GIC Parameter */
#define PLAT_BRCM_GICD_BASE GIC500_BASE
#define PLAT_BRCM_GICR_BASE (GIC500_BASE + 0x200000)
/* Define secure interrupt as per Group here */
#define PLAT_BRCM_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(BRCM_IRQ_SEC_SPI_0, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE)
#define PLAT_BRCM_G0_IRQ_PROPS(grp) \
INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
GIC_INTR_CFG_EDGE), \
/*
*CCN 502 related constants.
*/
#define PLAT_BRCM_CLUSTER_COUNT 4 /* Number of RN-F Masters */
#define PLAT_BRCM_CLUSTER_TO_CCN_ID_MAP CLUSTER0_NODE_ID, CLUSTER1_NODE_ID, CLUSTER2_NODE_ID, CLUSTER3_NODE_ID
#define CCN_SIZE 0x1000000
#define CLUSTER0_NODE_ID 1
#define CLUSTER1_NODE_ID 7
#define CLUSTER2_NODE_ID 9
#define CLUSTER3_NODE_ID 15
#endif

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/*
* Copyright (c) 2016-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SR_DEF_H
#define SR_DEF_H
#ifndef __ASSEMBLER__
#include <lib/mmio.h>
#endif
#include <common/interrupt_props.h>
#include <drivers/arm/gic_common.h>
#include <crmu_def.h>
/* Special value used to verify platform parameters from BL2 to BL3-1 */
#define BRCM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
#define MHB_BASE_ADDR 0x60000000
#define PLAT_BRCM_CCN_BASE 0x61000000
#define CORESIGHT_BASE_ADDR 0x62000000
#define SMMU_BASE 0x64000000
/* memory map entries*/
/* Grouping block device for bigger MMU region */
/* covers MHB, CNN, coresight, GIC, MMU, APB, CRMU */
#define PERIPH0_BASE MHB_BASE_ADDR
#define PERIPH0_SIZE 0x06d00000
#define PERIPH1_BASE 0x66d80000
#define PERIPH1_SIZE 0x00f80000
#define HSLS_BASE_ADDR 0x68900000
#define HSLS_SIZE 0x04500000
#define GIC500_BASE 0x63c00000
#define GIC500_SIZE 0x400000
/*******************************************************************************
* CCN related constants
******************************************************************************/
#define OLY_MN_REGISTERS_NODE0_SECURE_ACCESS (PLAT_BRCM_CCN_BASE + 0x0)
#define OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL (PLAT_BRCM_CCN_BASE + 0x880500)
/* Used for acceleration of coherent ordered writes */
#define OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL_WUO BIT(4)
/* Wait for completion of requests at RN-I */
#define OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL_WFC BIT(3)
/*
* Forces all reads from the RN-I to be sent with the request order bit set
* and this ensures ordered allocation of read data buffers in the RN-I
*/
#define OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL_RQO BIT(5)
#define OLY_RNI3PDVM_REGISTERS_NODE14_AUX_CTL (PLAT_BRCM_CCN_BASE + 0x8e0500)
/* Wait for completion of requests at RN-I */
#define OLY_RNI3PDVM_REGISTERS_NODE14_AUX_CTL_WFC BIT(3)
#define OLY_HNI_REGISTERS_NODE0_POS_CONTROL (PLAT_BRCM_CCN_BASE + 0x80000)
#define POS_CONTROL_HNI_POS_EN BIT(0)
#define OLY_HNI_REGISTERS_NODE0_PCIERC_RNI_NODEID_LIST \
(PLAT_BRCM_CCN_BASE + 0x80008)
/* PAXB and PAXC connected to 8th Node */
#define SR_RNI_PCIE_CONNECTED BIT(8)
/* PAXB connected to 6th Node */
#define SRP_RNI_PCIE_CONNECTED BIT(6)
#define OLY_HNI_REGISTERS_NODE0_SA_AUX_CTL (PLAT_BRCM_CCN_BASE + 0x80500)
#define SA_AUX_CTL_POS_EARLY_WR_COMP_EN BIT(5)
#define SA_AUX_CTL_SER_DEVNE_WR BIT(9)
/*******************************************************************************
* Coresight related constants
******************************************************************************/
#define CORESIGHT_BASE_ADDR 0x62000000
#define IHOST0_BASE 0x66000000
#define IHOST_ADDR_SPACE 0x2000
/*******************************************************************************
* SCR related constants
******************************************************************************/
#define SCR_BASE 0x6600a000
#define SCR_ARCACHE_OFFSET 4
#define SCR_ARCACHE_MASK (0x3 << SCR_ARCACHE_OFFSET)
#define SCR_AWCACHE_OFFSET 6
#define SCR_AWCACHE_MASK (0x3 << SCR_AWCACHE_OFFSET)
#define SCR_AXCACHE_CONFIG_MASK (SCR_ARCACHE_MASK | SCR_AWCACHE_MASK)
#define SCR_TBUX_AXCACHE_CONFIG ((0x1 << SCR_AWCACHE_OFFSET) | \
(0x1 << SCR_ARCACHE_OFFSET))
#define SCR_REGS_SCR_SOFT_RESET (SCR_BASE + 0x1c)
#define SCR_REGS_GIC_SOFT_RESET BIT(0)
#define SCR_GPV_BASE 0x66100000
#define SCR_NOC_SECURITY0 (SCR_GPV_BASE + 0x08)
#define SCR_NOC_DDR_REGISTER_ACCESS (SCR_GPV_BASE + 0x30)
/*******************************************************************************
* MEMC and DDR related constants
******************************************************************************/
#define DDR0_CONTROL_ROOT 0x66200000
#define EMEM_SS_CFG_0_ROOT 0x66202000
#define EMEM_SYS_IF_0_ROOT 0x66204000
#define DDR_PHY0_ROOT 0x66240000
#define DDR1_CONTROL_ROOT 0x66280000
#define EMEM_SS_CFG_1_ROOT 0x66282000
#define EMEM_SYS_IF_1_ROOT 0x66284000
#define DDR_PHY1_ROOT 0x662c0000
#define DDR2_CONTROL_ROOT 0x66300000
#define EMEM_SS_CFG_2_ROOT 0x66302000
#define EMEM_SYS_IF_2_ROOT 0x66304000
#define DDR_PHY2_ROOT 0x66340000
/*******************************************************************************
* TZC400 related constants
******************************************************************************/
#define TZC_400_BASE 0x66d84000
/*******************************************************************************
* FS4 related constants
******************************************************************************/
#define FS4_SRAM_IDM_IO_CONTROL_DIRECT 0x66d8a408
#define FS4_CRYPTO_IDM_IO_CONTROL_DIRECT 0x66d8e408
#define FS4_CRYPTO_IDM_RESET_CONTROL 0x66d8e800
#define FS4_CRYPTO_BASE 0x67000000
#define FS4_CRYPTO_DME_BASE (FS4_CRYPTO_BASE + 0x280000)
#define FS4_RAID_IDM_IO_CONTROL_DIRECT 0x66d8f408
#define FS4_RAID_IDM_IO_STATUS 0x66d8f500
#define FS4_RAID_IDM_RESET_CONTROL 0x66d8f800
#define FS4_RAID_BASE 0x67400000
#define FS4_RAID_DME_BASE (FS4_RAID_BASE + 0x280000)
#define FS4_CRYPTO_GPV_BASE 0x67300000
#define FS4_RAID_GPV_BASE 0x67700000
#define FS6_PKI_BASE 0x67400000
#define FS6_PKI_DME_BASE 0x66D90000
#define TZC400_FS_SRAM_ROOT 0x66d84000
#define GATE_KEEPER_OFFSET 0x8
#define REGION_ATTRIBUTES_0_OFFSET 0x110
#define REGION_ID_ACCESS_0_OFFSET 0x114
#define NIC400_FS_NOC_ROOT 0x66e00000
#define NIC400_FS_NOC_SECURITY2_OFFSET 0x10
#define NIC400_FS_NOC_SECURITY4_OFFSET 0x18
#define NIC400_FS_NOC_SECURITY7_OFFSET 0x24
/*******************************************************************************
* SATA PHY related constants
******************************************************************************/
#define SATA_BASE 0x67d00000
/*******************************************************************************
* USB related constants
******************************************************************************/
#define USB_BASE 0x68500000
#define USB_SIZE 0x00400000
#define XHC_BASE (USB_BASE + 0x11000)
#define MAX_USB_PORTS 3
/*******************************************************************************
* HSLS related constants
******************************************************************************/
#define IPROC_ROOT 0x68900000
#define HSLS_ICFG_REGS_BASE IPROC_ROOT
#define HSLS_IDM_REGS_BASE 0x68e00000
#define HSLS_MODE_SEL_CONTROL 0x68a40000
#define HSLS_TZPC_BASE 0x68b40000
#define HSLS_GPV_BASE 0x6cd00000
/*******************************************************************************
* Chip ID related constants
******************************************************************************/
#define ICFG_CHIP_ID HSLS_ICFG_REGS_BASE
#define CHIP_ID_SR 0xd730
#define CHIP_ID_NS3Z 0xe56d
#define CHIP_ID_MASK 0xf000
#define ICFG_CHIP_REVISION_ID (HSLS_ICFG_REGS_BASE + 0x4)
#define PLAT_CHIP_ID_GET (mmio_read_32(ICFG_CHIP_ID))
#define PLAT_CHIP_REV_GET (mmio_read_32(ICFG_CHIP_REVISION_ID))
/*******************************************************************************
* Timers related constants
******************************************************************************/
/* ChipcommonG_tim0_TIM_TIMER1Load 0x68930000 */
#define SP804_TIMER0_BASE 0x68930000
#define SP804_TIMER1_BASE 0x68940000
#define SP804_TIMER0_TIMER_VAL_REG_OFFSET 0x4
#define SP804_TIMER0_CLKMULT 2
#define SP804_TIMER0_CLKDIV 25
/*******************************************************************************
* GPIO related constants
******************************************************************************/
#define IPROC_GPIO_NS_BASE 0x689d0000
#define IPROC_GPIO_S_BASE 0x68b00000
#define IPROC_GPIO_NR 151
#define GPIO_S_CNTRL_REG 0x68b60000
/*******************************************************************************
* I2C SMBUS related constants
******************************************************************************/
#define SMBUS0_REGS_BASE 0x689b0000
#define SMBUS1_REGS_BASE 0x689e0000
/*******************************************************************************
* UART related constants
******************************************************************************/
#define ChipcommonG_UART0_UART_RBR_THR_DLL 0x68a00000
#define ChipcommonG_UART1_UART_RBR_THR_DLL 0x68a10000
#define ChipcommonG_UART2_UART_RBR_THR_DLL 0x68a20000
#define ChipcommonG_UART3_UART_RBR_THR_DLL 0x68a30000
#define UART0_BASE_ADDR ChipcommonG_UART0_UART_RBR_THR_DLL
#define UART1_BASE_ADDR ChipcommonG_UART1_UART_RBR_THR_DLL
#define UART2_BASE_ADDR ChipcommonG_UART2_UART_RBR_THR_DLL
#define UART3_BASE_ADDR ChipcommonG_UART3_UART_RBR_THR_DLL
#define UART_SPR_OFFSET 0x1c /* Scratch Pad Register */
#define LOG_LEVEL_REGISTER CRMU_SPARE_REG_3
#define GET_LOG_LEVEL() (mmio_read_32(LOG_LEVEL_REGISTER))
#define SET_LOG_LEVEL(x) (mmio_write_32(LOG_LEVEL_REGISTER, x))
#define IO_RETRY_REGISTER CRMU_SPARE_REG_4
#define DWC_UART_REFCLK (25 * 1000 * 1000)
#define DWC_UART_REFCLK_DIV 16
/* Baud rate in emulation will vary based on setting of 25MHz SCLK */
#define DWC_UART_BAUDRATE 115200
#define BRCM_CRASH_CONSOLE_BASE UART1_BASE_ADDR
#define BRCM_CRASH_CONSOLE_REFCLK DWC_UART_REFCLK
#define BRCM_CRASH_CONSOLE_BAUDRATE DWC_UART_BAUDRATE
#ifdef BOARD_CONSOLE_UART
#define PLAT_BRCM_BOOT_UART_BASE BOARD_CONSOLE_UART
#else
#define PLAT_BRCM_BOOT_UART_BASE UART1_BASE_ADDR
#endif
#define CONSOLE_UART_ID ((PLAT_BRCM_BOOT_UART_BASE >> 16) & 0x3)
#define PLAT_BRCM_BOOT_UART_CLK_IN_HZ DWC_UART_REFCLK
#define BRCM_CONSOLE_BAUDRATE DWC_UART_BAUDRATE
#define PLAT_BRCM_BL31_RUN_UART_BASE PLAT_BRCM_BOOT_UART_BASE
#define PLAT_BRCM_BL31_RUN_UART_CLK_IN_HZ PLAT_BRCM_BOOT_UART_CLK_IN_HZ
/*******************************************************************************
* IOMUX related constants
******************************************************************************/
#define HSLS_IOPAD_BASE HSLS_MODE_SEL_CONTROL
#define MODE_SEL_CONTROL_FSEL_MASK 0x7
#define MODE_SEL_CONTROL_FSEL_MODE0 0x0
#define MODE_SEL_CONTROL_FSEL_MODE1 0x1
#define MODE_SEL_CONTROL_FSEL_MODE2 0x2
#define MODE_SEL_CONTROL_FSEL_MODE3 0x3
#define MODE_SEL_CONTROL_FSEL_DEBUG 0x4
#define IPROC_IOPAD_MODE_BASE (HSLS_MODE_SEL_CONTROL + 0x29c)
#define UART0_SIN_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x4a8)
#define UART0_SOUT_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x4ac)
#define UART1_SIN_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3b8)
#define UART1_SOUT_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3bc)
#define UARTx_SIN_MODE_SEL_CONTROL_FSEL 0
#define UARTx_SOUT_MODE_SEL_CONTROL_FSEL 0
/*******************************************************************************
* PKA constants
******************************************************************************/
#define ICFG_PKA_MEM_PWR_CTRL (HSLS_ICFG_REGS_BASE + 0xac0)
#define ICFG_PKA_MEM_PWR_CTRL__POWERONIN BIT(0)
#define ICFG_PKA_MEM_PWR_CTRL__POWEROKIN BIT(1)
#define ICFG_PKA_MEM_PWR_CTRL__ARRPOWERONIN BIT(2)
#define ICFG_PKA_MEM_PWR_CTRL__ARRPOWEROKIN BIT(3)
#define ICFG_PKA_MEM_PWR_CTRL__POWERONOUT BIT(4)
#define ICFG_PKA_MEM_PWR_CTRL__POWEROKOUT BIT(5)
#define ICFG_PKA_MEM_PWR_CTRL__ARRPOWERONOUT BIT(6)
#define ICFG_PKA_MEM_PWR_CTRL__ARRPOWEROKOUT BIT(7)
#define ICFG_PKA_MEM_PWR_CTRL__ISO BIT(8)
/*******************************************************************************
* Trusted Watchdog constants
******************************************************************************/
#define ARM_SP805_TWDG_BASE 0x68b30000
#define ARM_SP805_TWDG_CLK_HZ ((25 * 1000 * 1000) / 2)
/*
* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
* asserts reset after two consecutive countdowns (2 x 128 = 256 sec)
*/
#define ARM_TWDG_TIMEOUT_SEC 128
#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
ARM_TWDG_TIMEOUT_SEC)
/*******************************************************************************
* SOTP related constants
******************************************************************************/
#define SOTP_REGS_OTP_BASE 0x68b50000
#define SOTP_CHIP_CTRL (SOTP_REGS_OTP_BASE + 0x4c)
#define SOTP_CLEAR_SYSCTRL_ALL_MASTER_NS 0
/*******************************************************************************
* DMAC/PL330 related constants
******************************************************************************/
#define DMAC_M0_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x408)
#define BOOT_MANAGER_NS BIT(25)
#define DMAC_M0_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0x800)
#define ICFG_DMAC_CONFIG_0 (HSLS_ICFG_REGS_BASE + 0x190)
#define ICFG_DMAC_CONFIG_1 (HSLS_ICFG_REGS_BASE + 0x194)
#define ICFG_DMAC_CONFIG_2 (HSLS_ICFG_REGS_BASE + 0x198)
#define BOOT_PERIPHERAL_NS 0xffffffff
#define ICFG_DMAC_CONFIG_3 (HSLS_ICFG_REGS_BASE + 0x19c)
#define BOOT_IRQ_NS 0x0000ffff
#define ICFG_DMAC_SID_ARADDR_CONTROL (HSLS_ICFG_REGS_BASE + 0xaf0)
#define ICFG_DMAC_SID_AWADDR_CONTROL (HSLS_ICFG_REGS_BASE + 0xaf4)
#define ICFG_DMAC_MEM_PWR_CTRL__POWERONIN BIT(0)
#define ICFG_DMAC_MEM_PWR_CTRL__POWEROKIN BIT(1)
#define ICFG_DMAC_MEM_PWR_CTRL__ARRPOWERONIN BIT(2)
#define ICFG_DMAC_MEM_PWR_CTRL__ARRPOWEROKIN BIT(3)
#define ICFG_DMAC_MEM_PWR_CTRL__POWERONOUT BIT(4)
#define ICFG_DMAC_MEM_PWR_CTRL__POWEROKOUT BIT(5)
#define ICFG_DMAC_MEM_PWR_CTRL__ARRPOWERONOUT BIT(6)
#define ICFG_DMAC_MEM_PWR_CTRL__ARRPOWEROKOUT BIT(7)
#define ICFG_DMAC_MEM_PWR_CTRL__ISO BIT(8)
#define ICFG_DMAC_MEM_PWR_CTRL (HSLS_ICFG_REGS_BASE + 0xadc)
/*******************************************************************************
* PNOR related constants
******************************************************************************/
#define PNOR_ICFG_BASE (HSLS_ICFG_REGS_BASE + 0x780)
#define PNOR_ICFG_CS_0 PNOR_ICFG_BASE
#define PNOR_ICFG_CS_1 (PNOR_ICFG_BASE + 0x4)
#define PNOR_ICFG_CS_2 (PNOR_ICFG_BASE + 0x8)
#define PNOR_ICFG_CS_x_MASK0_MASK 0xff
#define PNOR_ICFG_CS_x_MASK0_SHIFT 8
#define PNOR_ICFG_CS_x_MATCH0_MASK 0xff
#define PNOR_ICFG_CS_x_MATCH0_SHIFT 0
#define PNOR_IDM_BASE (HSLS_IDM_REGS_BASE + 0xb000)
#define PNOR_IDM_IO_CONTROL_DIRECT (PNOR_IDM_BASE + 0x408)
#define PNOR_IDM_IO_RESET_CONTROL (PNOR_IDM_BASE + 0x800)
#define PNOR_REG_BASE 0x68c50000
#define PNOR_REG_DIRECT_CMD (PNOR_REG_BASE + 0x010)
#define PNOR_REG_SET_CYCLES (PNOR_REG_BASE + 0x014)
#define PNOR_REG_SET_OPMODE (PNOR_REG_BASE + 0x018)
#define PNOR_REG_REFRESH_0 (PNOR_REG_BASE + 0x020)
#define PNOR_REG_PERIPH_ID0 (PNOR_REG_BASE + 0xfe0)
#define PNOR_REG_PERIPH_ID1 (PNOR_REG_BASE + 0xfe4)
#define PNOR_REG_PERIPH_ID2 (PNOR_REG_BASE + 0xfe8)
#define PNOR_REG_PERIPH_ID3 (PNOR_REG_BASE + 0xfec)
#define PNOR_REG_PERIPH_IDx_MASK 0xff
/*******************************************************************************
* NAND related constants
******************************************************************************/
#define NAND_FLASH_REVISION 0x68c60000
#define NAND_IDM_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0xa408)
#define NAND_IDM_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0xa800)
/*******************************************************************************
* eMMC related constants
******************************************************************************/
#define PLAT_SD_MAX_READ_LENGTH 0x400
#define SDIO0_EMMCSDXC_SYSADDR 0x68cf1000
#define SDIO_IDM0_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x2408)
#define SDIO_IDM1_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x3408)
#define SDIO_IDM0_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0x2800)
#define ICFG_SDIO0_BASE (HSLS_ICFG_REGS_BASE + 0x6e4)
#define ICFG_SDIO1_BASE (HSLS_ICFG_REGS_BASE + 0x734)
#define ICFG_SDIO0_CAP0 (ICFG_SDIO0_BASE + 0x10)
#define ICFG_SDIO0_CAP1 (ICFG_SDIO0_BASE + 0x14)
#define ICFG_SDIO0_SID (HSLS_ICFG_REGS_BASE + 0xb00)
#define ICFG_SDIO1_SID (HSLS_ICFG_REGS_BASE + 0xb08)
/*******************************************************************************
* Bootstrap related constants
******************************************************************************/
#define ROM_S0_IDM_IO_STATUS (HSLS_IDM_REGS_BASE + 0x9500)
/*******************************************************************************
* ROM related constants
******************************************************************************/
#define ROM_BASE_ADDR 0x6ce00000
#define ROM_VERSION_STRING_ADDR (ROM_BASE_ADDR + 0x28000)
#define ROM_BUILD_MESSAGE_ADDR (ROM_BASE_ADDR + 0x28018)
/*******************************************************************************
* Boot source peripheral related constants
******************************************************************************/
#define QSPI_CTRL_BASE_ADDR 0x68c70000
#define QSPI_BASE_ADDR 0x70000000
#define QSPI_SIZE 0x08000000
#define NOR_BASE_ADDR 0x74000000
#define NOR_SIZE 0x04000000
#define NAND_BASE_ADDR 0x78000000
#define NAND_SIZE 0x08000000
#define QSPI_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0xc800)
#define APBR_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0xe800)
#define APBS_IDM_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0xf800)
#define APBX_IDM_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x10408)
#define APBX_IDM_IDM_IO_CONTROL_DIRECT_CLK_ENABLE 0
#define APBX_IDM_IDM_IO_CONTROL_DIRECT_WDOG_SCLK_SEL 2
#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM0_SCLK_SEL 4
#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM1_SCLK_SEL 6
#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM2_SCLK_SEL 8
#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM3_SCLK_SEL 10
#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM4_SCLK_SEL 12
#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM5_SCLK_SEL 13
#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM6_SCLK_SEL 14
#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM7_SCLK_SEL 15
#define APBY_IDM_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x11408)
#define APBY_IDM_IDM_IO_CONTROL_DIRECT_CLK_ENABLE 0
#define APBY_IDM_IDM_IO_CONTROL_DIRECT_UART0_SCLK_SEL 2
#define APBY_IDM_IDM_IO_CONTROL_DIRECT_UART1_SCLK_SEL 4
#define APBY_IDM_IDM_IO_CONTROL_DIRECT_UART2_SCLK_SEL 6
#define APBY_IDM_IDM_IO_CONTROL_DIRECT_UART3_SCLK_SEL 8
#define APBZ_IDM_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x12408)
#define APBZ_IDM_IDM_IO_CONTROL_DIRECT_CLK_ENABLE 0
#define APBZ_IDM_IDM_IO_CONTROL_DIRECT_WDOG_SCLK_SEL 2
/*******************************************************************************
* Stingray memory map related constants
******************************************************************************/
/* The last 4KB of Trusted SRAM are used as shared memory */
#define BRCM_SHARED_RAM_SIZE 0x0
#define BRCM_SHARED_RAM_BASE (PLAT_BRCM_TRUSTED_SRAM_BASE + \
PLAT_BRCM_TRUSTED_SRAM_SIZE - \
BRCM_SHARED_RAM_SIZE)
/* Reserve 4 KB to store error logs in BL2 */
#define BCM_ELOG_BL2_SIZE 0x00001000
#define BCM_ELOG_BL2_BASE BL1_RW_LIMIT
/* The remaining Trusted SRAM is used to load the BL images */
#define BRCM_BL_RAM_BASE (PLAT_BRCM_TRUSTED_SRAM_BASE)
#define BRCM_BL_RAM_SIZE (PLAT_BRCM_TRUSTED_SRAM_SIZE - \
BRCM_SHARED_RAM_SIZE)
/* DDR Address where TMON temperature values are written */
#define TMON_SHARED_DDR_ADDRESS 0x8f100000
/* Reserve 4 kB to pass data to BL33 */
#define BL33_SHARED_DDR_BASE 0x8f102000
#define BL33_SHARED_DDR_SIZE 0x1000
/* Default AP error logging base addr */
#ifndef ELOG_AP_UART_LOG_BASE
#define ELOG_AP_UART_LOG_BASE 0x8f110000
#endif
/* Reserve 16 to store error logs in BL31 */
#define BCM_ELOG_BL31_BASE ELOG_AP_UART_LOG_BASE
#define BCM_ELOG_BL31_SIZE 0x4000
/*******************************************************************************
* Non-secure DDR Map
******************************************************************************/
#define BRCM_DRAM1_BASE ULL(0x80000000)
#define BRCM_DRAM1_SIZE ULL(0x10000000)
#define BRCM_DRAM2_BASE ULL(0x880000000)
#define BRCM_DRAM2_SIZE ULL(0x780000000)
#define BRCM_DRAM3_BASE ULL(0x8800000000)
#define BRCM_DRAM3_SIZE ULL(0x7800000000)
#define BRCM_SHARED_DRAM_BASE BL33_SHARED_DDR_BASE
#define BRCM_SHARED_DRAM_SIZE BL33_SHARED_DDR_SIZE
#define BRCM_EXT_SRAM_BASE ULL(0x74000000)
#define BRCM_EXT_SRAM_SIZE ULL(0x4000000)
/* Priority levels for platforms */
#define PLAT_RAS_PRI 0x10
#define PLAT_SDEI_CRITICAL_PRI 0x60
#define PLAT_SDEI_NORMAL_PRI 0x70
/* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 */
#define BRCM_IRQ_SEC_SGI_0 14
#define BRCM_IRQ_SEC_SGI_1 15
/* RTC periodic interrupt */
#define BRCM_IRQ_SEC_SPI_0 49
/*
* Macros for local power states in SR platforms encoded by State-ID field
* within the power-state parameter.
*/
/* Local power state for power domains in Run state. */
#define PLAT_LOCAL_STATE_RUN 0
/* Local power state for retention. Valid only for CPU power domains */
#define PLAT_LOCAL_STATE_RET 1
/*
* Local power state for OFF/power-down. Valid for CPU and cluster power
* domains.
*/
#define PLAT_LOCAL_STATE_OFF 2
/*
* This macro defines the deepest retention state possible. A higher state
* id will represent an invalid or a power down state.
*/
#define PLAT_MAX_RET_STATE PLAT_LOCAL_STATE_RET
/*
* This macro defines the deepest power down states possible. Any state ID
* higher than this is invalid.
*/
#define PLAT_MAX_OFF_STATE PLAT_LOCAL_STATE_OFF
/* ChiMP-related constants */
#define NITRO_TZPC_TZPCDECPROT0clr 0x60c01808
#define NITRO_TZPC_TZPCDECPROT0clr__DECPROT0_chimp_m_clr_R 1
#define NIC400_NITRO_CHIMP_S_IDM_IO_CONTROL_DIRECT 0x60e00408
#define CHIMP_INDIRECT_ADDR_MASK 0x3fffff
#define CHIMP_INDIRECT_BASE 0x60800000
#define CHIMP_REG_ECO_RESERVED 0x3042400
#define CHIMP_FLASH_ACCESS_DONE_BIT 2
/* indicate FRU table programming is done successfully */
#define CHIMP_FRU_PROG_DONE_BIT 9
#define CHIMP_REG_CTRL_BPE_MODE_REG 0x0
#define CHIMP_REG_CTRL_BPE_STAT_REG 0x4
#define CHIMP_REG_CTRL_FSTBOOT_PTR_REG 0x8
#define CHIMP_REG_CHIMP_REG_CTRL_BPE_MODE_REG__cm3_rst_L 1
#define CHIMP_REG_CHIMP_REG_CTRL_BPE_MODE_REG__cm3_rst_R 1
#define CHIMP_REG_CTRL_BASE 0x3040000
#define CHIMP_FAST_BOOT_MODE_BIT 2
#define CHIMP_REG_CHIMP_APE_SCPAD 0x3300000
#define CHIMP_REG_CHIMP_SCPAD 0x3100000
/* Chimp health status offset in scratch pad ram */
#define CHIMP_HEALTH_STATUS_OFFSET 0x8
/*
* If not in NIC mode then FASTBOOT can be enabled.
* "Not in NIC mode" means that FORCE_FASTBOOT is set
* and a valid (1 or 2) fastboot type is specified.
*
* Three types of fastboot are supported:
* 0 = No fastboot. Boots Nitro/ChiMP and lets ROM loader
* initialize ChiMP from NVRAM (QSPI).
*
* 1 = Jump in place (need a flat image)
* This is intended to speedup Nitro FW boot on Palladium,
* can be used with a real chip as well.
* 2 = Jump normally with decompression
* Modus operandi for a real chip. Works also on Palladium
* Note: image decompressing takes time on Palladium.
* 3 = No fastboot support. No ChiMP bringup
* (use only for AP debug or for ChiMP's deferred setup).
*/
#define CHIMP_FASTBOOT_JUMP_DECOMPRESS 2
#define CHIMP_FASTBOOT_JUMP_IN_PLACE 1
#define CHIMP_FASTBOOT_NITRO_RESET 0
/*
* Definitions for a non-Nitro access
* to QSPI PAD after the handshake
*/
#define QSPI_HOLD_N_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3e8)
#define QSPI_WP_N_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3ec)
#define QSPI_SCK_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3f0)
#define QSPI_CS_N_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3f4)
#define QSPI_MOSI_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3f8)
#define QSPI_MISO_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3fc)
/*******************************************************************************
* Stream IDs for different blocks of SR
* block_id for different blocks is as follows:
* PCIE : 0x0
* PAXC : 0x1
* FS4 : 0x2
* Rest of the masters(includes MHB via RNI): 0x3
******************************************************************************/
#define SR_SID_VAL(block_id, subblock_id, device_num) ((block_id << 13) | \
(subblock_id << 11) | \
(device_num))
#define CRMU_STREAM_ID SR_SID_VAL(0x3, 0x0, 0x7)
#define CRMU_SID_SHIFT 5
#define DMAC_STREAM_ID SR_SID_VAL(0x3, 0x0, 0x0)
#define DMAC_SID_SHIFT 5
/* DDR SHMOO Values defines */
#define IDRAM_SHMOO_VALUES_ADDR CRMU_IDRAM_BASE_ADDR
#define DDR_SHMOO_VALUES_ADDR 0x8f103000
#define SHMOO_SIZE_PER_CHANNEL 0x1000
#endif /* SR_DEF_H */

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#
# Copyright (c) 2019-2020, Broadcom
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Enable workaround for ERRATA_A72_859971
ERRATA_A72_859971 := 1
# Cache Coherency Interconnect Driver needed
DRIVER_CC_ENABLE := 1
$(eval $(call add_define,DRIVER_CC_ENABLE))
USE_CRMU_SRAM := yes
# Use single cluster
ifeq (${USE_SINGLE_CLUSTER},yes)
$(info Using Single Cluster)
$(eval $(call add_define,USE_SINGLE_CLUSTER))
endif
ifeq (${BOARD_CFG},)
BOARD_CFG := bcm958742k
endif
# For testing purposes, use memsys stubs. Remove once memsys is fully tested.
USE_MEMSYS_STUBS := yes
# Default, use BL1_RW area
ifneq (${BL2_USE_BL1_RW},no)
$(eval $(call add_define,USE_BL1_RW))
endif
# Default soft reset is L3
$(eval $(call add_define,CONFIG_SOFT_RESET_L3))
include plat/brcm/board/common/board_common.mk
SOC_DIR := brcm/board/stingray
PLAT_INCLUDES += -Iplat/${SOC_DIR}/include/ \
-Iinclude/plat/brcm/common/ \
-Iplat/brcm/common/
PLAT_BL_COMMON_SOURCES += lib/cpus/aarch64/cortex_a72.S \
plat/${SOC_DIR}/aarch64/plat_helpers.S \
drivers/ti/uart/aarch64/16550_console.S \
drivers/arm/tzc/tzc400.c

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/*
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/bl_common.h>
#include <common/desc_image_load.h>
#include <plat/common/platform.h>
#include <platform_def.h>
/*******************************************************************************
* Following descriptor provides BL image/ep information that gets used
* by BL2 to load the images and also subset of this information is
* passed to next BL image. The image loading sequence is managed by
* populating the images in required loading order. The image execution
* sequence is managed by populating the `next_handoff_image_id` with
* the next executable image id.
******************************************************************************/
static bl_mem_params_node_t bl2_mem_params_descs[] = {
#ifdef SCP_BL2_BASE
/* Fill SCP_BL2 related information if it exists */
{
.image_id = SCP_BL2_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_2, image_info_t, 0),
.image_info.image_base = SCP_BL2_BASE,
.image_info.image_max_size = PLAT_MAX_SCP_BL2_SIZE,
.next_handoff_image_id = INVALID_IMAGE_ID,
},
#endif /* SCP_BL2_BASE */
/* Fill BL31 related information */
{
.image_id = BL31_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
SECURE | EXECUTABLE | EP_FIRST_EXE),
.ep_info.pc = BL31_BASE,
.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS),
#if DEBUG
.ep_info.args.arg3 = BRCM_BL31_PLAT_PARAM_VAL,
#endif
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
.image_info.image_base = BL31_BASE,
.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
#ifdef BL32_BASE
.next_handoff_image_id = BL32_IMAGE_ID,
#else
.next_handoff_image_id = BL33_IMAGE_ID,
#endif
},
#ifdef BL32_BASE
/* Fill BL32 related information */
{
.image_id = BL32_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
.ep_info.pc = BL32_BASE,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
.image_info.image_base = BL32_BASE,
.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
.next_handoff_image_id = BL33_IMAGE_ID,
},
#endif /* BL32_BASE */
/* Fill BL33 related information */
{
.image_id = BL33_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
#ifdef PRELOADED_BL33_BASE
.ep_info.pc = PRELOADED_BL33_BASE,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
#else
.ep_info.pc = PLAT_BRCM_NS_IMAGE_OFFSET,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
.image_info.image_base = PLAT_BRCM_NS_IMAGE_OFFSET,
.image_info.image_max_size = BRCM_DRAM1_SIZE,
#endif /* PRELOADED_BL33_BASE */
.next_handoff_image_id = INVALID_IMAGE_ID,
}
};
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)

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/*
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <string.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
#include <drivers/arm/sp804_delay_timer.h>
#include <lib/mmio.h>
#include <bcm_console.h>
#include <platform_def.h>
#include <plat/brcm/common/plat_brcm.h>
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
/* Weak definitions may be overridden in specific BRCM platform */
#pragma weak plat_bcm_bl2_platform_setup
#pragma weak plat_bcm_bl2_plat_arch_setup
#pragma weak plat_bcm_security_setup
#pragma weak plat_bcm_bl2_plat_handle_scp_bl2
#pragma weak plat_bcm_bl2_early_platform_setup
void plat_bcm_bl2_early_platform_setup(void)
{
}
void plat_bcm_bl2_platform_setup(void)
{
}
void plat_bcm_bl2_plat_arch_setup(void)
{
}
void plat_bcm_security_setup(void)
{
}
void bcm_bl2_early_platform_setup(uintptr_t tb_fw_config,
meminfo_t *mem_layout)
{
/* Initialize the console to provide early debug support */
bcm_console_boot_init();
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
/* Initialise the IO layer and register platform IO devices */
plat_brcm_io_setup();
/* Log HW reset event */
INFO("RESET: 0x%x\n",
mmio_read_32(CRMU_RESET_EVENT_LOG));
}
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
/* SoC specific setup */
plat_bcm_bl2_early_platform_setup();
/* Initialize delay timer driver using SP804 dual timer 0 */
sp804_timer_init(SP804_TIMER0_BASE,
SP804_TIMER0_CLKMULT, SP804_TIMER0_CLKDIV);
/* BRCM platforms generic setup */
bcm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
}
/*
* Perform Broadcom platform setup.
*/
void bcm_bl2_platform_setup(void)
{
/* Initialize the secure environment */
plat_bcm_security_setup();
}
void bl2_platform_setup(void)
{
bcm_bl2_platform_setup();
plat_bcm_bl2_platform_setup();
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/
void bcm_bl2_plat_arch_setup(void)
{
#ifndef MMU_DISABLED
if (!(read_sctlr_el1() & SCTLR_M_BIT)) {
const mmap_region_t bl_regions[] = {
MAP_REGION_FLAT(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(BL_CODE_BASE,
BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE),
MAP_REGION_FLAT(BL_RO_DATA_BASE,
BL_RO_DATA_END - BL_RO_DATA_BASE,
MT_RO_DATA | MT_SECURE),
#if USE_COHERENT_MEM
MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END -
BL_COHERENT_RAM_BASE,
MT_DEVICE | MT_RW | MT_SECURE),
#endif
{0}
};
setup_page_tables(bl_regions, plat_brcm_get_mmap());
enable_mmu_el1(0);
}
#endif
}
void bl2_plat_arch_setup(void)
{
#ifdef ENA_MMU_BEFORE_DDR_INIT
/*
* Once MMU is enabled before DDR, MEMORY TESTS
* get affected as read/write transaction might occures from
* caches. So For running memory test, one should not set this
* flag.
*/
bcm_bl2_plat_arch_setup();
plat_bcm_bl2_plat_arch_setup();
#else
plat_bcm_bl2_plat_arch_setup();
bcm_bl2_plat_arch_setup();
#endif
}
int bcm_bl2_handle_post_image_load(unsigned int image_id)
{
int err = 0;
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
assert(bl_mem_params);
switch (image_id) {
case BL32_IMAGE_ID:
bl_mem_params->ep_info.spsr = brcm_get_spsr_for_bl32_entry();
break;
case BL33_IMAGE_ID:
/* BL33 expects to receive the primary CPU MPID (through r0) */
bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
bl_mem_params->ep_info.spsr = brcm_get_spsr_for_bl33_entry();
break;
#ifdef SCP_BL2_BASE
case SCP_BL2_IMAGE_ID:
/* The subsequent handling of SCP_BL2 is platform specific */
err = bcm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
if (err)
WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
break;
#endif
default:
/* Do nothing in default case */
break;
}
return err;
}
/*******************************************************************************
* This function can be used by the platforms to update/use image
* information for given `image_id`.
******************************************************************************/
int bcm_bl2_plat_handle_post_image_load(unsigned int image_id)
{
return bcm_bl2_handle_post_image_load(image_id);
}
int bl2_plat_handle_post_image_load(unsigned int image_id)
{
return bcm_bl2_plat_handle_post_image_load(image_id);
}
#ifdef SCP_BL2_BASE
int plat_bcm_bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info)
{
return 0;
}
int bcm_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
{
return plat_bcm_bl2_plat_handle_scp_bl2(scp_bl2_image_info);
}
#endif

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/*
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <plat/common/platform.h>
#include <plat_brcm.h>
#include <platform_def.h>
/* Weak definitions may be overridden in specific BRCM platform */
#pragma weak plat_get_ns_image_entrypoint
#pragma weak plat_brcm_get_mmap
uintptr_t plat_get_ns_image_entrypoint(void)
{
#ifdef PRELOADED_BL33_BASE
return PRELOADED_BL33_BASE;
#else
return PLAT_BRCM_NS_IMAGE_OFFSET;
#endif
}
uint32_t brcm_get_spsr_for_bl32_entry(void)
{
/*
* The Secure Payload Dispatcher service is responsible for
* setting the SPSR prior to entry into the BL32 image.
*/
return 0;
}
uint32_t brcm_get_spsr_for_bl33_entry(void)
{
unsigned int mode;
uint32_t spsr;
/* Figure out what mode we enter the non-secure world in */
mode = el_implemented(2) ? MODE_EL2 : MODE_EL1;
/*
* TODO: Consider the possibility of specifying the SPSR in
* the FIP ToC and allowing the platform to have a say as
* well.
*/
spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
const mmap_region_t *plat_brcm_get_mmap(void)
{
return plat_brcm_mmap;
}

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/*
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/bl_common.h>
#include <common/desc_image_load.h>
#include <plat/common/platform.h>
#pragma weak plat_flush_next_bl_params
#pragma weak plat_get_bl_image_load_info
#pragma weak plat_get_next_bl_params
/*******************************************************************************
* This function flushes the data structures so that they are visible
* in memory for the next BL image.
******************************************************************************/
void plat_flush_next_bl_params(void)
{
flush_bl_params_desc();
}
/*******************************************************************************
* This function returns the list of loadable images.
******************************************************************************/
struct bl_load_info *plat_get_bl_image_load_info(void)
{
return get_bl_load_info_from_mem_params_desc();
}
/*******************************************************************************
* This function returns the list of executable images.
******************************************************************************/
struct bl_params *plat_get_next_bl_params(void)
{
bl_params_t *next_bl_params = get_next_bl_params_from_mem_params_desc();
populate_next_bl_params_config(next_bl_params);
return next_bl_params;
}

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/*
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <string.h>
#include <common/debug.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_fip.h>
#include <drivers/io/io_memmap.h>
#include <drivers/io/io_storage.h>
#include <tools_share/firmware_image_package.h>
#include <cmn_plat_def.h>
#include <cmn_plat_util.h>
#include <plat_brcm.h>
#include <platform_def.h>
/* IO devices */
static const io_dev_connector_t *fip_dev_con;
static uintptr_t fip_dev_handle;
static const io_dev_connector_t *memmap_dev_con;
static uintptr_t memmap_dev_handle;
static const io_block_spec_t fip_block_spec = {
.offset = PLAT_BRCM_FIP_BASE,
.length = PLAT_BRCM_FIP_MAX_SIZE
};
static const io_block_spec_t qspi_fip_block_spec = {
.offset = PLAT_BRCM_FIP_QSPI_BASE,
.length = PLAT_BRCM_FIP_MAX_SIZE
};
static const io_block_spec_t nand_fip_block_spec = {
.offset = PLAT_BRCM_FIP_NAND_BASE,
.length = PLAT_BRCM_FIP_MAX_SIZE
};
static const io_uuid_spec_t bl2_uuid_spec = {
.uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
};
static const io_uuid_spec_t scp_bl2_uuid_spec = {
.uuid = UUID_SCP_FIRMWARE_SCP_BL2,
};
static const io_uuid_spec_t bl31_uuid_spec = {
.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
};
static const io_uuid_spec_t bl32_uuid_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32,
};
static const io_uuid_spec_t bl32_extra1_uuid_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1,
};
static const io_uuid_spec_t bl32_extra2_uuid_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
};
static const io_uuid_spec_t bl33_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
static const io_uuid_spec_t tb_fw_config_uuid_spec = {
.uuid = UUID_TB_FW_CONFIG,
};
static const io_uuid_spec_t hw_config_uuid_spec = {
.uuid = UUID_HW_CONFIG,
};
static const io_uuid_spec_t soc_fw_config_uuid_spec = {
.uuid = UUID_SOC_FW_CONFIG,
};
static const io_uuid_spec_t tos_fw_config_uuid_spec = {
.uuid = UUID_TOS_FW_CONFIG,
};
static const io_uuid_spec_t nt_fw_config_uuid_spec = {
.uuid = UUID_NT_FW_CONFIG,
};
#if TRUSTED_BOARD_BOOT
static const io_uuid_spec_t tb_fw_cert_uuid_spec = {
.uuid = UUID_TRUSTED_BOOT_FW_CERT,
};
static const io_uuid_spec_t trusted_key_cert_uuid_spec = {
.uuid = UUID_TRUSTED_KEY_CERT,
};
static const io_uuid_spec_t scp_fw_key_cert_uuid_spec = {
.uuid = UUID_SCP_FW_KEY_CERT,
};
static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = {
.uuid = UUID_SOC_FW_KEY_CERT,
};
static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = {
.uuid = UUID_TRUSTED_OS_FW_KEY_CERT,
};
static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FW_KEY_CERT,
};
static const io_uuid_spec_t scp_fw_cert_uuid_spec = {
.uuid = UUID_SCP_FW_CONTENT_CERT,
};
static const io_uuid_spec_t soc_fw_cert_uuid_spec = {
.uuid = UUID_SOC_FW_CONTENT_CERT,
};
static const io_uuid_spec_t tos_fw_cert_uuid_spec = {
.uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT,
};
static const io_uuid_spec_t nt_fw_cert_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT,
};
#endif /* TRUSTED_BOARD_BOOT */
static int open_fip(const uintptr_t spec);
static int open_memmap(const uintptr_t spec);
static int open_qspi(const uintptr_t spec);
static int open_nand(const uintptr_t spec);
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
int (*check)(const uintptr_t spec);
};
/* By default, BRCM platforms load images from the FIP */
static const struct plat_io_policy policies[] = {
[FIP_IMAGE_ID] = {
&memmap_dev_handle,
(uintptr_t)&fip_block_spec,
open_memmap
},
[BL2_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl2_uuid_spec,
open_fip
},
[SCP_BL2_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&scp_bl2_uuid_spec,
open_fip
},
[BL31_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl31_uuid_spec,
open_fip
},
[BL32_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl32_uuid_spec,
open_fip
},
[BL32_EXTRA1_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl32_extra1_uuid_spec,
open_fip
},
[BL32_EXTRA2_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl32_extra2_uuid_spec,
open_fip
},
[BL33_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl33_uuid_spec,
open_fip
},
[TB_FW_CONFIG_ID] = {
&fip_dev_handle,
(uintptr_t)&tb_fw_config_uuid_spec,
open_fip
},
[HW_CONFIG_ID] = {
&fip_dev_handle,
(uintptr_t)&hw_config_uuid_spec,
open_fip
},
[SOC_FW_CONFIG_ID] = {
&fip_dev_handle,
(uintptr_t)&soc_fw_config_uuid_spec,
open_fip
},
[TOS_FW_CONFIG_ID] = {
&fip_dev_handle,
(uintptr_t)&tos_fw_config_uuid_spec,
open_fip
},
[NT_FW_CONFIG_ID] = {
&fip_dev_handle,
(uintptr_t)&nt_fw_config_uuid_spec,
open_fip
},
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&tb_fw_cert_uuid_spec,
open_fip
},
[TRUSTED_KEY_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&trusted_key_cert_uuid_spec,
open_fip
},
[SCP_FW_KEY_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&scp_fw_key_cert_uuid_spec,
open_fip
},
[SOC_FW_KEY_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&soc_fw_key_cert_uuid_spec,
open_fip
},
[TRUSTED_OS_FW_KEY_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&tos_fw_key_cert_uuid_spec,
open_fip
},
[NON_TRUSTED_FW_KEY_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&nt_fw_key_cert_uuid_spec,
open_fip
},
[SCP_FW_CONTENT_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&scp_fw_cert_uuid_spec,
open_fip
},
[SOC_FW_CONTENT_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&soc_fw_cert_uuid_spec,
open_fip
},
[TRUSTED_OS_FW_CONTENT_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&tos_fw_cert_uuid_spec,
open_fip
},
[NON_TRUSTED_FW_CONTENT_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&nt_fw_cert_uuid_spec,
open_fip
},
#endif /* TRUSTED_BOARD_BOOT */
};
/* By default, BRCM platforms load images from the FIP */
static const struct plat_io_policy boot_source_policies[] = {
[BOOT_SOURCE_QSPI] = {
&memmap_dev_handle,
(uintptr_t)&qspi_fip_block_spec,
open_qspi
},
[BOOT_SOURCE_NAND] = {
&memmap_dev_handle,
(uintptr_t)&nand_fip_block_spec,
open_nand
},
};
/* Weak definitions may be overridden in specific brcm platform */
#pragma weak plat_brcm_io_setup
#pragma weak plat_brcm_process_flags
static int open_fip(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
/* See if a Firmware Image Package is available */
result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
if (result == 0) {
result = io_open(fip_dev_handle, spec, &local_image_handle);
if (result == 0) {
VERBOSE("Using FIP\n");
io_close(local_image_handle);
}
}
return result;
}
static int open_memmap(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
if (result == 0) {
result = io_open(memmap_dev_handle, spec, &local_image_handle);
if (result == 0) {
VERBOSE("Using Memmap\n");
io_close(local_image_handle);
}
}
return result;
}
static int open_qspi(const uintptr_t spec)
{
return open_memmap(spec);
}
static int open_nand(const uintptr_t spec)
{
return open_memmap(spec);
}
void brcm_io_setup(void)
{
int io_result;
uint32_t boot_source;
io_result = register_io_dev_fip(&fip_dev_con);
assert(io_result == 0);
io_result = register_io_dev_memmap(&memmap_dev_con);
assert(io_result == 0);
/* Open connections to devices and cache the handles */
io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
&fip_dev_handle);
assert(io_result == 0);
boot_source = boot_source_get();
switch (boot_source) {
case BOOT_SOURCE_QSPI:
case BOOT_SOURCE_NAND:
default:
io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
&memmap_dev_handle);
break;
}
assert(io_result == 0);
/* Ignore improbable errors in release builds */
(void)io_result;
}
void plat_brcm_io_setup(void)
{
brcm_io_setup();
}
void plat_brcm_process_flags(uint16_t plat_toc_flags __unused)
{
WARN("%s not implemented\n", __func__);
}
/*
* Return an IO device handle and specification which can be used to access
* an image. Use this to enforce platform load policy
*/
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec)
{
int result;
const struct plat_io_policy *policy;
uint32_t boot_source;
uint16_t lcl_plat_toc_flg;
assert(image_id < ARRAY_SIZE(policies));
boot_source = boot_source_get();
if (image_id == FIP_IMAGE_ID)
policy = &boot_source_policies[boot_source];
else
policy = &policies[image_id];
result = policy->check(policy->image_spec);
if (result == 0) {
*image_spec = policy->image_spec;
*dev_handle = *(policy->dev_handle);
if (image_id == TRUSTED_BOOT_FW_CERT_ID) {
/*
* Process the header flags to perform
* such custom actions as speeding up PLL.
* CERT seems to be the first image accessed
* by BL1 so this is where we process the flags.
*/
fip_dev_get_plat_toc_flag((io_dev_info_t *)fip_dev_handle,
&lcl_plat_toc_flg);
plat_brcm_process_flags(lcl_plat_toc_flg);
}
}
return result;
}