From 718dbcac9c36c51a1527ed298fba6fa5ee88632f Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Mon, 12 Oct 2020 18:13:07 +0300 Subject: [PATCH] plat/marvell/armada: allow builds without MSS support Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2 definition. Images build with MSS_SUPPORT=0 will not include service CPUs FW and will not support PM, FC and other features implemented in these FW images. Signed-off-by: Konstantin Porotchkin Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769 Tested-by: sa_ip-sw-jenkins Reviewed-by: Stefan Chulski Reviewed-by: Ofer Heifetz Reviewed-by: Nadav Haklai --- docs/plat/marvell/armada/build.rst | 2 +- drivers/marvell/comphy/phy-comphy-cp110.c | 13 +++++++++---- plat/marvell/armada/a8k/common/a8k_common.mk | 11 +++++++++-- plat/marvell/armada/a8k/common/plat_bl31_setup.c | 7 ++++++- plat/marvell/armada/a8k/common/plat_pm.c | 15 ++++++++++++--- plat/marvell/armada/a8k/common/plat_pm_trace.c | 4 +++- 6 files changed, 40 insertions(+), 12 deletions(-) diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index e55ce3c09..948e87b4f 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -26,7 +26,7 @@ BL33 should be ``~/project/u-boot/u-boot.bin`` *u-boot.bin* should be used and not *u-boot-spl.bin* -Set MSS/SCP image path (mandatory only for A7K/8K/CN913x) +Set MSS/SCP image path (mandatory only for A7K/8K/CN913x when MSS_SUPPORT=1) .. code:: shell diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c index d1c26f8d3..51d3c4c92 100644 --- a/drivers/marvell/comphy/phy-comphy-cp110.c +++ b/drivers/marvell/comphy/phy-comphy-cp110.c @@ -2284,7 +2284,6 @@ static int mvebu_cp110_comphy_ap_power_on(uint64_t comphy_base, uint32_t comphy_mode) { uint32_t mask, data; - uint8_t ap_nr, cp_nr; uintptr_t comphy_addr = comphy_addr = COMPHY_ADDR(comphy_base, comphy_index); @@ -2301,10 +2300,16 @@ static int mvebu_cp110_comphy_ap_power_on(uint64_t comphy_base, reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); debug_exit(); - /* Start AP Firmware */ - mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base); - mg_start_ap_fw(cp_nr, comphy_index); +#if MSS_SUPPORT + do { + uint8_t ap_nr, cp_nr; + /* start ap fw */ + mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base); + mg_start_ap_fw(cp_nr, comphy_index); + + } while (0); +#endif return 0; } diff --git a/plat/marvell/armada/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk index 3acc3b4cf..90883f285 100644 --- a/plat/marvell/armada/a8k/common/a8k_common.mk +++ b/plat/marvell/armada/a8k/common/a8k_common.mk @@ -10,13 +10,14 @@ PLAT_COMMON_BASE := plat/marvell/armada/a8k/common MARVELL_DRV_BASE := drivers/marvell MARVELL_COMMON_BASE := plat/marvell/armada/common -MARVELL_SVC_TEST := 0 +MARVELL_SVC_TEST := 0 $(eval $(call add_define,MARVELL_SVC_TEST)) ERRATA_A72_859971 := 1 # Enable MSS support for a8k family MSS_SUPPORT := 1 +$(eval $(call add_define,MSS_SUPPORT)) # Disable EL3 cache for power management BL31_CACHE_DISABLE := 0 @@ -114,12 +115,15 @@ MARVELL_DRV := $(MARVELL_DRV_BASE)/io_win.c \ $(MARVELL_DRV_BASE)/cache_llc.c \ $(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \ $(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c \ - $(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c \ $(MARVELL_DRV_BASE)/secure_dfx_access/armada_thermal.c \ $(MARVELL_DRV_BASE)/secure_dfx_access/misc_dfx.c \ $(MARVELL_DRV_BASE)/ddr_phy_access.c \ drivers/rambus/trng_ip_76.c +ifeq (${MSS_SUPPORT}, 1) +MARVELL_DRV += $(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c +endif + BL31_PORTING_SOURCES := $(BOARD_DIR)/board/marvell_plat_config.c ifeq ($(SYSTEM_POWER_SUPPORT),1) @@ -142,6 +146,8 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \ # Add trace functionality for PM BL31_SOURCES += $(PLAT_COMMON_BASE)/plat_pm_trace.c + +ifeq (${MSS_SUPPORT}, 1) # Force builds with BL2 image on a80x0 platforms ifndef SCP_BL2 $(error "Error: SCP_BL2 image is mandatory for a8k family") @@ -149,6 +155,7 @@ endif # MSS (SCP) build include $(PLAT_COMMON_BASE)/mss/mss_a8k.mk +endif # BLE (ROM context execution code, AKA binary extension) BLE_PATH ?= $(PLAT_COMMON_BASE)/ble diff --git a/plat/marvell/armada/a8k/common/plat_bl31_setup.c b/plat/marvell/armada/a8k/common/plat_bl31_setup.c index 552c9b298..50dcd2891 100644 --- a/plat/marvell/armada/a8k/common/plat_bl31_setup.c +++ b/plat/marvell/armada/a8k/common/plat_bl31_setup.c @@ -16,8 +16,10 @@ #include #include #include +#if MSS_SUPPORT #include #include +#endif /* In Armada-8k family AP806/AP807, CP0 connected to PIDI * and CP1 connected to IHB via MCI #0 @@ -51,6 +53,7 @@ static void marvell_bl31_mpp_init(int cp) mmio_write_32(MVEBU_CP_MPP_REGS(0, 4), reg | 0x2200000); } +#if MSS_SUPPORT void marvell_bl31_mss_init(void) { struct mss_pm_ctrl_block *mss_pm_crtl = @@ -70,6 +73,7 @@ void marvell_bl31_mss_init(void) if (mss_pm_crtl->ipc_state == IPC_INITIALIZED) mv_pm_ipc_init(mss_pm_crtl->ipc_base_address | MVEBU_REGS_BASE); } +#endif _Bool is_pm_fw_running(void) { @@ -125,11 +129,12 @@ void bl31_plat_arch_setup(void) for (cp = 1; cp < CP_COUNT; cp++) mci_link_tune(cp - 1); +#if MSS_SUPPORT /* initialize IPC between MSS and ATF */ if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM || mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) marvell_bl31_mss_init(); - +#endif /* Configure GPIO */ marvell_gpio_config(); diff --git a/plat/marvell/armada/a8k/common/plat_pm.c b/plat/marvell/armada/a8k/common/plat_pm.c index 96e95c271..9ea927608 100644 --- a/plat/marvell/armada/a8k/common/plat_pm.c +++ b/plat/marvell/armada/a8k/common/plat_pm.c @@ -18,7 +18,9 @@ #include #include +#if MSS_SUPPORT #include +#endif #include #include @@ -396,6 +398,7 @@ static int a8k_pwr_domain_on(u_register_t mpidr) /* Power up CPU (CPUs 1-3 are powered off at start of BLE) */ plat_marvell_cpu_powerup(mpidr); +#if MSS_SUPPORT if (is_pm_fw_running()) { unsigned int target = ((mpidr & 0xFF) + (((mpidr >> 8) & 0xFF) * 2)); @@ -417,11 +420,12 @@ static int a8k_pwr_domain_on(u_register_t mpidr) /* trace message */ PM_TRACE(TRACE_PWR_DOMAIN_ON | target); - } else { + } else +#endif + { /* proprietary CPU ON exection flow */ plat_marvell_cpu_on(mpidr); } - return 0; } @@ -441,6 +445,7 @@ static int a8k_validate_ns_entrypoint(uintptr_t entrypoint) */ static void a8k_pwr_domain_off(const psci_power_state_t *target_state) { +#if MSS_SUPPORT if (is_pm_fw_running()) { unsigned int idx = plat_my_core_pos(); @@ -466,6 +471,7 @@ static void a8k_pwr_domain_off(const psci_power_state_t *target_state) } else { INFO("%s: is not supported without SCP\n", __func__); } +#endif } /* Get PM config to power off the SoC */ @@ -586,6 +592,7 @@ static void plat_marvell_power_off_prepare(struct power_off_method *pm_cfg, */ static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state) { +#if MSS_SUPPORT if (is_pm_fw_running()) { unsigned int idx; @@ -610,7 +617,9 @@ static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state) /* trace message */ PM_TRACE(TRACE_PWR_DOMAIN_SUSPEND); - } else { + } else +#endif + { uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; INFO("Suspending to RAM\n"); diff --git a/plat/marvell/armada/a8k/common/plat_pm_trace.c b/plat/marvell/armada/a8k/common/plat_pm_trace.c index f589ff31b..e02a89386 100644 --- a/plat/marvell/armada/a8k/common/plat_pm_trace.c +++ b/plat/marvell/armada/a8k/common/plat_pm_trace.c @@ -8,10 +8,11 @@ #include #include +#if MSS_SUPPORT #include -#include #ifdef PM_TRACE_ENABLE +#include /* core trace APIs */ core_trace_func funcTbl[PLATFORM_CORE_COUNT] = { @@ -90,3 +91,4 @@ void pm_core_3_trace(unsigned int trace) AP_MSS_ATF_TRACE_SIZE_MASK)); } #endif /* PM_TRACE_ENABLE */ +#endif /* MSS_SUPPORT */