arm_fpga: Add support for topology self-discovery
As secondary cores show up, they populate an array to announce themselves so plat_core_pos_by_mpidr() can return an invalid COREID code for any non-existing MPIDR that it is queried about. The Power Domain Tree Description is populated with a topology based on the maximum harcoded values. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I8fd64761a2296714ce0f37c46544f3e6f13b5f61
This commit is contained in:
Javier Almansa Sobrino
parent
1056ddce76
commit
727bbf680d
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@ -7,6 +7,8 @@
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include "../fpga_private.h"
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#include <platform_def.h>
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.globl plat_get_my_entrypoint
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@ -14,10 +16,10 @@
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.globl plat_is_my_cpu_primary
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.globl platform_mem_init
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.globl plat_my_core_pos
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.globl plat_fpga_calc_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl plat_fpga_calc_core_pos
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/* -----------------------------------------------------------------------
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* Indicate a cold boot for every CPU - warm boot is unsupported for the
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@ -34,23 +36,59 @@ endfunc plat_get_my_entrypoint
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* -----------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/*
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* Wait for the primary processor to initialise the .BSS segment
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* to avoid a race condition that would erase fpga_valid_mpids
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* if it is populated before the C runtime is ready.
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*
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* We cannot use the current spin-lock implementation until the
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* runtime is up and we should not rely on sevl/wfe instructions as
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* it is optional whether they are implemented or not, so we use
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* a global variable as lock and wait for the primary processor to
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* finish the C runtime bring-up.
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*/
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ldr w0, =C_RUNTIME_READY_KEY
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adrp x1, secondary_core_spinlock
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add x1, x1, :lo12:secondary_core_spinlock
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1:
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wfe
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ldr w2, [x1]
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cmp w2, w0
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b.ne 1b
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/* Prevent reordering of the store into fpga_valid_mpids below */
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dmb ish
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mov x10, x30
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bl plat_my_core_pos
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mov x30, x10
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adrp x4, fpga_valid_mpids
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add x4, x4, :lo12:fpga_valid_mpids
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mov x5, #VALID_MPID
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strb w5, [x4, x0]
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/*
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* Poll the CPU's hold entry until it indicates to jump
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* to the entrypoint address.
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*/
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bl plat_my_core_pos
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lsl x0, x0, #PLAT_FPGA_HOLD_ENTRY_SHIFT
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ldr x1, =hold_base
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ldr x2, =fpga_sec_entrypoint
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adrp x1, hold_base
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add x1, x1, :lo12:hold_base
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poll_hold_entry:
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ldr x3, [x1, x0]
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ldr x3, [x1, x0, LSL #PLAT_FPGA_HOLD_ENTRY_SHIFT]
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cmp x3, #PLAT_FPGA_HOLD_STATE_GO
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b.ne 1f
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adrp x2, fpga_sec_entrypoint
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add x2, x2, :lo12:fpga_sec_entrypoint
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ldr x3, [x2]
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br x3
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1:
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wfe
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b poll_hold_entry
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endfunc plat_secondary_cold_boot_setup
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/* -----------------------------------------------------------------------
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@ -73,12 +111,16 @@ func platform_mem_init
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endfunc platform_mem_init
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func plat_my_core_pos
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ldr x1, =(MPID_MASK & ~(MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT))
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mrs x0, mpidr_el1
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and x0, x0, x1
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b plat_fpga_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------------------------
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* unsigned int plat_fpga_calc_core_pos(u_register_t mpidr)
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* unsigned int plat_fpga_calc_core_pos (uint32_t mpid)
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* Clobber registers: x0 to x5
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* -----------------------------------------------------------------------
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*/
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func plat_fpga_calc_core_pos
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@ -88,6 +130,7 @@ func plat_fpga_calc_core_pos
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*
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* If not set, shift MPIDR to left to make it look as if in a
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* multi-threaded implementation.
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*
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*/
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tst x0, #MPIDR_MT_MASK
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lsl x3, x0, #MPIDR_AFFINITY_BITS
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@ -98,11 +141,13 @@ func plat_fpga_calc_core_pos
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ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
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/* Compute linear position */
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mov x4, #FPGA_MAX_CPUS_PER_CLUSTER
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madd x1, x2, x4, x1
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mov x5, #FPGA_MAX_PE_PER_CPU
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/* Compute linear position */
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madd x1, x2, x4, x1
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madd x0, x1, x5, x0
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ret
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endfunc plat_fpga_calc_core_pos
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@ -7,23 +7,23 @@
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#include <assert.h>
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#include <common/fdt_wrappers.h>
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#include <drivers/delay_timer.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <libfdt.h>
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#include "fpga_private.h"
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include "fpga_private.h"
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static entry_point_info_t bl33_image_ep_info;
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volatile uint32_t secondary_core_spinlock;
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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#ifdef PRELOADED_BL33_BASE
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return PRELOADED_BL33_BASE;
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#else
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return 0;
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return 0ULL;
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#endif
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}
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@ -35,6 +35,17 @@ uint32_t fpga_get_spsr_for_bl33_entry(void)
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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/* Add this core to the VALID mpids list */
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fpga_valid_mpids[plat_my_core_pos()] = VALID_MPID;
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/*
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* Notify the secondary CPUs that the C runtime is ready
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* so they can announce themselves.
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*/
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secondary_core_spinlock = C_RUNTIME_READY_KEY;
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dsbish();
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sev();
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fpga_console_init();
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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@ -54,11 +65,37 @@ void bl31_plat_arch_setup(void)
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void bl31_platform_setup(void)
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{
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/* Initialize the GIC driver, cpu and distributor interfaces */
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plat_fpga_gic_init();
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/* Write frequency to CNTCRL and initialize timer */
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generic_delay_timer_init();
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/*
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* Before doing anything else, wait for some time to ensure that
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* the secondary CPUs have populated the fpga_valid_mpids array.
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* As the number of secondary cores is unknown and can even be 0,
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* it is not possible to rely on any signal from them, so use a
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* delay instead.
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*/
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mdelay(5);
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/*
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* On the event of a cold reset issued by, for instance, a reset pin
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* assertion, we cannot guarantee memory to be initialized to zero.
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* In such scenario, if the secondary cores reached
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* plat_secondary_cold_boot_setup before the primary one initialized
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* .BSS, we could end up having a race condition if the spinlock
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* was not cleared before.
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*
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* Similarly, if there were a reset before the spinlock had been
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* cleared, the secondary cores would find the lock opened before
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* .BSS is cleared, causing another race condition.
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*
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* So clean the spinlock as soon as we think it is safe to reduce the
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* chances of any race condition on a reset.
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*/
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secondary_core_spinlock = 0UL;
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/* Initialize the GIC driver, cpu and distributor interfaces */
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plat_fpga_gic_init();
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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@ -18,6 +18,7 @@
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* that are present will still be indexed appropriately regardless of any empty
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* entries in the array used to represent the topology.
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*/
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#define FPGA_MAX_CLUSTER_COUNT 4
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#define FPGA_MAX_CPUS_PER_CLUSTER 8
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#define FPGA_MAX_PE_PER_CPU 4
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@ -7,12 +7,23 @@
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#ifndef FPGA_PRIVATE_H
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#define FPGA_PRIVATE_H
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unsigned int plat_fpga_calc_core_pos(u_register_t mpidr);
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#include "../fpga_def.h"
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#include <platform_def.h>
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#define C_RUNTIME_READY_KEY (0xaa55aa55)
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#define VALID_MPID (1U)
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#ifndef __ASSEMBLER__
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extern unsigned char fpga_valid_mpids[PLATFORM_CORE_COUNT];
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void fpga_console_init(void);
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void plat_fpga_gic_init(void);
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void fpga_pwr_gic_on_finish(void);
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void fpga_pwr_gic_off(void);
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unsigned int plat_fpga_calc_core_pos(uint32_t mpid);
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#endif
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#endif /* __ASSEMBLER__ */
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#endif /* FPGA_PRIVATE_H */
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@ -5,15 +5,20 @@
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/spinlock.h>
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#include "fpga_private.h"
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#include <plat/common/platform.h>
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#include <platform_def.h>
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static unsigned char fpga_power_domain_tree_desc[FPGA_MAX_CLUSTER_COUNT + 2];
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unsigned char fpga_power_domain_tree_desc[FPGA_MAX_CLUSTER_COUNT + 2];
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unsigned char fpga_valid_mpids[PLATFORM_CORE_COUNT];
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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int i;
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unsigned int i;
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/*
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* The highest level is the system level. The next level is constituted
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* by clusters and then cores in clusters.
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@ -21,12 +26,26 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
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* This description of the power domain topology is aligned with the CPU
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* indices returned by the plat_core_pos_by_mpidr() and plat_my_core_pos()
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* APIs.
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*
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* A description of the topology tree can be found at
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* https://trustedfirmware-a.readthedocs.io/en/latest/design/psci-pd-tree.html#design
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*/
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fpga_power_domain_tree_desc[0] = 1;
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fpga_power_domain_tree_desc[1] = FPGA_MAX_CLUSTER_COUNT;
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for (i = 0; i < FPGA_MAX_CLUSTER_COUNT; i++) {
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fpga_power_domain_tree_desc[i + 2] = FPGA_MAX_CPUS_PER_CLUSTER * FPGA_MAX_PE_PER_CPU;
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if (fpga_power_domain_tree_desc[0] == 0U) {
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/*
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* As fpga_power_domain_tree_desc[0] == 0, assume that the
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* Power Domain Topology Tree has not been initialized, so
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* perform the initialization here.
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*/
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fpga_power_domain_tree_desc[0] = 1U;
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fpga_power_domain_tree_desc[1] = FPGA_MAX_CLUSTER_COUNT;
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for (i = 0U; i < FPGA_MAX_CLUSTER_COUNT; i++) {
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fpga_power_domain_tree_desc[2 + i] =
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(FPGA_MAX_CPUS_PER_CLUSTER *
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FPGA_MAX_PE_PER_CPU);
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}
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}
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return fpga_power_domain_tree_desc;
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@ -34,40 +53,25 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int cluster_id, cpu_id, thread_id;
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unsigned int core_pos;
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/*
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* The image running on the FPGA may or may not implement
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* multithreading, and it shouldn't be assumed this is consistent
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* across all CPUs.
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* This ensures that any passed mpidr values reflect the status of the
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* primary CPU's MT bit.
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*/
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mpidr &= (MPID_MASK & ~(MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT));
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mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
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mpidr &= MPID_MASK;
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if (mpidr & MPIDR_MT_MASK) {
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thread_id = MPIDR_AFFLVL0_VAL(mpidr);
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cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
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cluster_id = MPIDR_AFFLVL2_VAL(mpidr);
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} else {
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thread_id = 0;
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cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
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if ((MPIDR_AFFLVL2_VAL(mpidr) >= FPGA_MAX_CLUSTER_COUNT) ||
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(MPIDR_AFFLVL1_VAL(mpidr) >= FPGA_MAX_CPUS_PER_CLUSTER) ||
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(MPIDR_AFFLVL0_VAL(mpidr) >= FPGA_MAX_PE_PER_CPU)) {
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ERROR ("Invalid mpidr: 0x%08x\n", (uint32_t)mpidr);
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panic();
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}
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if (cluster_id >= FPGA_MAX_CLUSTER_COUNT) {
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/* Calculate the core position, based on the maximum topology. */
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core_pos = plat_fpga_calc_core_pos(mpidr);
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/* Check whether this core is actually present. */
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if (fpga_valid_mpids[core_pos] != VALID_MPID) {
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return -1;
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}
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if (cpu_id >= FPGA_MAX_CPUS_PER_CLUSTER) {
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return -1;
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}
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if (thread_id >= FPGA_MAX_PE_PER_CPU) {
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return -1;
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}
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/* Calculate the correct core, catering for multi-threaded images */
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return (int) plat_fpga_calc_core_pos(mpidr);
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return core_pos;
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}
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@ -21,11 +21,12 @@
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#define CACHE_WRITEBACK_SHIFT U(6)
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#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
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#define PLATFORM_CORE_COUNT \
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(FPGA_MAX_CLUSTER_COUNT * FPGA_MAX_CPUS_PER_CLUSTER * FPGA_MAX_PE_PER_CPU)
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#define PLATFORM_CORE_COUNT \
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(FPGA_MAX_CLUSTER_COUNT * \
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FPGA_MAX_CPUS_PER_CLUSTER * \
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FPGA_MAX_PE_PER_CPU)
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#define PLAT_NUM_PWR_DOMAINS (FPGA_MAX_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT) + 1
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#define PLAT_NUM_PWR_DOMAINS (FPGA_MAX_CLUSTER_COUNT + PLATFORM_CORE_COUNT + 1)
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#if !ENABLE_PIE
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#define BL31_BASE UL(0x80000000)
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